app: perf_overlay: add note on CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT

On many Intel platforms, the HD-DMA interrupts can interfere with component level performance measurements. Add a comment how to disable the interrupts when doing component performance analysis. Signed-off-by: Kai Vehmanen <[email protected]>
kv2019i · Nov 19, 2024 · 36894e8 · 36894e8
1 parent ccc3429
commit 36894e8
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diff --git a/app/perf_overlay.conf b/app/perf_overlay.conf
@@ -8,3 +8,9 @@ CONFIG_ADSP_IDLE_CLOCK_GATING=n
 CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL=n
 # disable top-level statistics to reduce logging overhead
 CONFIG_SCHEDULE_LL_STATS_LOG=n
+
+# vendor/target dependent options
+#
+# uncomment to disable Intel HD-DMA L1 exit ISR. this affects
+# the peak execution times at component level
+#CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT=n
diff --git a/app/prj.conf b/app/prj.conf
@@ -53,3 +53,5 @@ CONFIG_SCHED_CPU_MASK_PIN_ONLY=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=15000
 CONFIG_DAI=y
 CONFIG_HEAP_MEM_POOL_SIZE=2048
+
+CONFIG_DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT=n