This page displays the test programmes used to verify our design and the resultant outputs seen on the waveform viewer that prooves the correctness of our CPU design implemnetation working as per the needs of this course work.
In addition, we have also added videos that show the outputs for the F1 Program driving the neopixel bar on VBuddy and the trace values for the Reference Program plotted on the VBuddy's TFT display.
The program developed and used by the team:
main:
jal a1, iloop
addi a2, zero, 0x0
beq a2, zero, 0
iloop:
lb a0, 0(zero)
lb a0, 1(zero)
lb a0, 2(zero)
lb a0, 3(zero)
lb a0, 4(zero)
lb a0, 5(zero)
lb a0, 6(zero)
lb a0, 7(zero)
nop
nop
nop
lb a0, 8(zero)
jalr a3, a1, 0
mloop:
beq a2, zero, mloop
Resultant waveform view from the risc_v.vcd file:
Outputs from a0 driving the neopixel bar on VBuddy:
F1_Light_VBuddy.2.3.mp4
To test, go to the rtl folder and run source doit.sh.
Resultant waveform view from the risc_v.vcd file:
Having entered _loop3, a0 will start taking the values at mem[base_pdf+a1). The next line of instruction increments a1 by 1, causing a0 to take the value at the next address. This loop will keep repeating itself until the end of the pdf array.
gaussian.mp4
noisy.mp4
triangle.mp4
sine.mp4
The waveform views for all were displayed as expected. When testing on the Vbuddy, the Sine and Triangle did not seem like sine and triangle waves. However, since the Gaussian and Noisy was displayed perfectly, and the waveforms are displayed as it should, we believe the CPU is working correctly.