- ๐ป Iโm interested in FPGA Digital Design, HPC Software Dev and Computer Architecture.
- FPGAs : Latency/Throughput driven designs, Resource/Target Aware Neural Network mappings, Custom Mathematical Function Acceleration.
- HPC Software : Concurrency, Distributed Systems, Parallel computing (Using GPUs, SIMD Vectorisation, Software to ASIC)
- Computer Arch : Hardware Aware Compiler Optimisations, Profile Guided Optimisations, Application Specific CPU/SoC Design (Ex: Tesla Dojo, Signal Processing MCUs/DSPs)
- ๐ Experienced Languages: C/C++, Python, SystemVerilog/Verilog, Maxeler (Hardware Design DSL), Bash
- ๐ฌ Experienced Tools: Intel Quartus, Intel VTune Profiler, Perf, Docker, Kubernetes, PyTorch/TensorFlow, Verilator/ModelSim.
- ๐ฑ Love reading science and medicine just to know more about who I am ๐จ, where we are ๐ and where we can go ๐.
- ๐ซ Reach me out for any questions!
๐ป
Electronic and Information (Computer) Engineering - Imperial College London
System Software Engineer - Nvidia
-
Nvidia
- London, United Kingdom
-
02:12
(UTC) - johanjino.github.io
- in/johan-jino-student
Highlights
- Pro
Pinned Loading
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ExecEngine_C_Compiler
ExecEngine_C_Compiler PublicANSI C to RISC-V assembly compiler as part of the EIE 2nd Year Instruction Set Architecture and Compilers coursework.
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RISC-V_CPU
RISC-V_CPU PublicRISC-V 32I CPU designed as part of the instruction set architecture (ISA) module for 2nd year EIE at Imperial College London.
C++
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MazeMaster
MazeMaster PublicAutonomous bot capable of balancing on two wheels that traverses through a maze formed using white LED strips and maps it on a webapp to find shortest path. This project was developed as part of thโฆ
Verilog
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sony/nmos-cpp
sony/nmos-cpp PublicAn NMOS (Networked Media Open Specifications) Registry and Node in C++ (IS-04, IS-05)
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NVIDIA/nvnmos
NVIDIA/nvnmos PublicNVIDIA NMOS (Networked Media Open Specifications) Library
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