Bringing the VGA internal signal to the top level (SpinalHDL#67 (comm…

…ent))
jmio · Oct 19, 2021 · d677cd6 · d677cd6
1 parent 819050b
commit d677cd6
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala b/hardware/scala/saxon/board/muselab/ICESugerPro/ICESugarProMinimal.scala
@@ -169,6 +169,7 @@ class ICESugarProMinimal extends Component{
     val phyA = Ecp5Sdrx2PhyGenerator().connect(sdramA)
     val hdmiPhy = vga.withHdmiEcp5(hdmiCd.outputClockDomain)
     val vgaPhy = vga.withRegisterPhy(withColorEn = false)
+    val vgaBus = Handle(vga.output.toIo)
 
     interconnect.setPipelining(bmbPeripheral.bmb)(cmdHalfRate = true, rspHalfRate = true)
     interconnect.setPipelining(cpu.dBus)(cmdValid = true)