revert riscv test

jfalcou · Sep 15, 2024 · af4d016 · af4d016
1 parent 30e375c
commit af4d016
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/include/eve/module/core/regular/impl/simd/riscv/logical_and.hpp b/include/eve/module/core/regular/impl/simd/riscv/logical_and.hpp
@@ -14,8 +14,8 @@
 namespace eve::detail
 {
   template<callable_options O, typename T, typename U, typename N>
-  EVE_FORCEINLINE logical<wide<T, N>> logical_and_(EVE_REQUIRES(cpu_), O const&, logical<wide<T, N>> v, logical<wide<U, N>> w) noexcept
-    // requires(rvv_abi<abi_t<T, N>> || rvv_abi<abi_t<U, N>>)
+  EVE_FORCEINLINE logical<wide<T, N>> logical_and_(EVE_REQUIRES(rvv_), O const&, logical<wide<T, N>> v, logical<wide<U, N>> w) noexcept
+    requires(rvv_abi<abi_t<T, N>> || rvv_abi<abi_t<U, N>>)
   {
     return __riscv_vmand(v, bit_cast(w, as<logical<wide<T, N>>>{}), N::value);
   }