Update submodule content (#66) · intel/rohd-website@fae4cba

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Update submodule content (#66)

Co-authored-by: mkorbel1 <[email protected]>

github-actions[bot] and mkorbel1 authored Jul 22, 2024

1 parent ebc1853 commit fae4cba

+1 −1		CHANGELOG.md
+3 −1		analysis_options.yaml
+40 −7		lib/src/module.dart
+18 −18		lib/src/modules/bus.dart
+1 −1		lib/src/modules/gates.dart
+2 −2		lib/src/selection.dart
+2 −2		lib/src/signals/logic.dart
+1 −1		lib/src/signals/logic_array.dart
+10 −0		lib/src/signals/logic_structure.dart
+140 −29		lib/src/synthesizers/systemverilog.dart
+1 −1		lib/src/utilities/simcompare.dart
+1 −1		lib/src/values/logic_value.dart
+6 −1		test/external_test.dart
+68 −0		test/module_test.dart
+5 −4		test/name_test.dart
+22 −0		test/sv_param_passthrough.sv
+131 −0		test/sv_param_passthrough_test.dart
+1 −7		test/translations_test.dart