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Pure hardware (VHDL) master with constant latency timestamp functionality test project

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icelinker/IEEE1588-Master-VHDL

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Hardware IEEE1588 Master

Test project to host pure hardware (VHDL) IEE1588 Master

Aim

Provide a simple, IEEE1588 Master with constant latency timestamp functionality

Requires

Firmware

NMEA Parser

git clone https://github.com/craighaywood/VHDL-NMEA-Parser

1588 Master IP Core

  • Please contact

Hardware

  • Numato Saturn (however project can easily be adapted to any FPGA board)
  • SIRF based GPS module (although NMEA parser can easily be adapted to other GPS, see NMEA parser project)

Results

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Pure hardware (VHDL) master with constant latency timestamp functionality test project

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