Final RIFFA 2.2.2 commit

hmaarrfk · Sep 7, 2016 · 4e9d3c8 · 4e9d3c8
1 parent f994e89
commit 4e9d3c8
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Showing 61 changed files with 211 additions and 147 deletions.
diff --git a/Makefile b/Makefile
@@ -42,7 +42,7 @@ include release.mk
 CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 RIFFA_ROOT_PATH := $(CURRENT_PATH)
 
-RELEASE_VER=2.2.1
+RELEASE_VER=2.2.2
 RELEASE_DIR=riffa_$(RELEASE_VER)
 RELEASE_PATH=$(CURRENT_PATH)/$(RELEASE_DIR)
 RELEASE_SRC_DIR=$(RELEASE_DIR)/source

diff --git a/fpga/altera/de2i/DE2Gen1x1If64/bit/DE2Gen1x1If64.sof b/fpga/altera/de2i/DE2Gen1x1If64/bit/DE2Gen1x1If64.sof
diff --git a/fpga/altera/de2i/DE2Gen1x1If64/prj/DE2Gen1x1If64.qsf b/fpga/altera/de2i/DE2Gen1x1If64/prj/DE2Gen1x1If64.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CGX150DF31C7
 set_global_assignment -name TOP_LEVEL_ENTITY DE2Gen1x1If64
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:52:42  MARCH 20, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

diff --git a/fpga/altera/de4/DE4Gen1x8If64/bit/DE4Gen1x8If64.sof b/fpga/altera/de4/DE4Gen1x8If64/bit/DE4Gen1x8If64.sof
diff --git a/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qsf b/fpga/altera/de4/DE4Gen1x8If64/prj/DE4Gen1x8If64.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4SGX230KF40C2
 set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen1x8If64
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13  MARCH 24, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -180,11 +180,11 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name SEARCH_PATH ../../../../riffa_hdl
 set_global_assignment -name QIP_FILE ../ip/ALTGXPCIeGen1x8.qip
 set_global_assignment -name QIP_FILE ../ip/ALTPLL50I50O125O250O.qip
 set_global_assignment -name QIP_FILE ../ip/PCIeGen1x8If64.qip
 set_global_assignment -name SDC_FILE ../constr/DE4Gen1x8If64.sdc
-set_global_assignment -name SEARCH_PATH ../../../../riffa_hdl
 set_global_assignment -name VERILOG_FILE ../hdl/DE4Gen1x8If64.v
 set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de4.v
 set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v

diff --git a/fpga/altera/de4/DE4Gen2x8If128/bit/DE4Gen2x8If128.sof b/fpga/altera/de4/DE4Gen2x8If128/bit/DE4Gen2x8If128.sof
diff --git a/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qsf b/fpga/altera/de4/DE4Gen2x8If128/prj/DE4Gen2x8If128.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4SGX230KF40C2
 set_global_assignment -name TOP_LEVEL_ENTITY DE4Gen2x8If128
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:13  MARCH 24, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

diff --git a/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf b/fpga/altera/de5/DE5Gen1x8If64/prj/DE5Gen1x8If64.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE 5SGXEA7N2F45C2
 set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen1x8If64
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 
 ################################################################################

diff --git a/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf b/fpga/altera/de5/DE5Gen2x8If128/prj/DE5Gen2x8If128.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE 5SGXEA7N2F45C2
 set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen2x8If128
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 
 ################################################################################

diff --git a/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf b/fpga/altera/de5/DE5Gen3x4If128/prj/DE5Gen3x4If128.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE 5SGXEA7N2F45C2
 set_global_assignment -name TOP_LEVEL_ENTITY DE5Gen3x4If128
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 
 ################################################################################

diff --git a/fpga/altera/de5/DE5QGen1x8If64/bit/DE5QGen1x8If64.sof b/fpga/altera/de5/DE5QGen1x8If64/bit/DE5QGen1x8If64.sof
diff --git a/fpga/altera/de5/DE5QGen1x8If64/prj/DE5QGen1x8If64.qsf b/fpga/altera/de5/DE5QGen1x8If64/prj/DE5QGen1x8If64.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE 5SGXEA7N2F45C2
 set_global_assignment -name TOP_LEVEL_ENTITY DE5QGen1x8If64
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 ################################################################################
 # Timing SDC Files

diff --git a/fpga/altera/de5/DE5QGen1x8If64_CLK/bit/DE5QGen1x8If64_CLK.sof b/fpga/altera/de5/DE5QGen1x8If64_CLK/bit/DE5QGen1x8If64_CLK.sof
diff --git a/fpga/altera/de5/DE5QGen2x8If128/bit/DE5QGen2x8If128.sof b/fpga/altera/de5/DE5QGen2x8If128/bit/DE5QGen2x8If128.sof
diff --git a/fpga/altera/de5/DE5QGen2x8If128/prj/DE5QGen2x8If128.qsf b/fpga/altera/de5/DE5QGen2x8If128/prj/DE5QGen2x8If128.qsf
@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE 5SGXEA7N2F45C2
 set_global_assignment -name TOP_LEVEL_ENTITY DE5QGen2x8If128
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:03:06  MARCH 21, 2014"
-set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ../bit/
 
 ################################################################################