fix reset on prev pr (#46)

gtaylormb · Jun 9, 2024 · ad3153f · ad3153f
1 parent 97051b4
commit ad3153f
Showing 1 changed file with 7 additions and 6 deletions.
diff --git a/fpga/modules/channels/src/channels.sv b/fpga/modules/channels/src/channels.sv
@@ -74,7 +74,7 @@ module channels
     logic cnt; // operator connection
     logic [REG_FB_WIDTH-1:0] fb_dummy;
 
-    always_ff @(posedge clk)
+    always_ff @(posedge clk) begin
         if (opl3_reg_wr.valid) begin
             if (opl3_reg_wr.bank_num == 1 && opl3_reg_wr.address == 4)
                 connection_sel <= opl3_reg_wr.data[REG_CONNECTION_SEL_WIDTH-1:0];
@@ -84,13 +84,14 @@ module channels
 
             if (opl3_reg_wr.bank_num == 0 && opl3_reg_wr.address == 'hBD)
                 ryt <= opl3_reg_wr.data[5];
+        end
 
-            if (reset) begin
-                // these should be reset as next game after reset may be OPL2 and not clear bank 1
-                connection_sel <= 0;
-                is_new <= 0;
-            end
+        if (reset) begin
+            // these should be reset as next game after reset may be OPL2 and not clear bank 1
+            connection_sel <= 0;
+            is_new <= 0;
         end
+    end
 
     mem_multi_bank #(
         .DATA_WIDTH(REG_FILE_DATA_WIDTH),