updates from ao486 (#33)

fpga/modules/channels/src/channels.sv

@@ -45,7 +45,7 @@ module channels
     import opl3_pkg::*;
 (
     input wire clk,
-    input wire clk_host,
+    input wire clk_dac,
     input var opl3_reg_wr_t opl3_reg_wr,
     input wire sample_clk_en,
     output logic sample_valid,

fpga/modules/channels/src/dac_prep.sv

@@ -45,7 +45,7 @@ module dac_prep
     import opl3_pkg::*;
 (
     input wire clk,
-    input wire clk_host,
+    input wire clk_dac,
     input wire channel_valid,
     input wire signed [SAMPLE_WIDTH-1:0] channel_l,
     input wire signed [SAMPLE_WIDTH-1:0] channel_r,
@@ -64,21 +64,29 @@ module dac_prep
     end
 
     generate
-    if (INSTANTIATE_SAMPLE_SYNC_TO_CPU_CLK) begin
+    if (INSTANTIATE_SAMPLE_SYNC_TO_DAC_CLK) begin
+        logic [2:0] sample_valid_opl3_pulse_extend;
+        logic sample_valid_opl3_extended_pulse = 0;
         logic sample_valid_cpu_p0;
         logic sample_valid_cpu_p1 = 0;
 
+        always_ff @(posedge clk) begin
+            sample_valid_opl3_pulse_extend <= sample_valid_opl3_pulse_extend << 1;
+            sample_valid_opl3_pulse_extend[0] <= sample_valid_opl3_p1;
+            sample_valid_opl3_extended_pulse <= sample_valid_opl3_pulse_extend != 0;
+        end
+
         synchronizer channel_valid_sync (
-            .clk(clk_host),
-            .in(sample_valid_opl3_p1),
+            .clk(clk_dac),
+            .in(sample_valid_opl3_extended_pulse),
             .out(sample_valid_cpu_p0)
         );
 
         /*
         * OPL3 channels are latched and held on channel_valid for a full sample period, so we only need to
         * synchronize the channel_valid bit and use to latch samples into cpu clock domain
         */
-        always_ff @(posedge clk_host) begin
+        always_ff @(posedge clk_dac) begin
             sample_valid_cpu_p1 <= sample_valid_cpu_p0;
 
             if (sample_valid_cpu_p0) begin

fpga/modules/host_if/src/host_if.sv

@@ -61,21 +61,17 @@ module host_if
     logic opl3_fifo_empty;
     logic [1:0] opl3_address;
     logic [REG_FILE_DATA_WIDTH-1:0] opl3_data;
-
     logic wr;
-    logic wr_p1 = 0;
 
     always_comb wr = !cs_n && !wr_n;
 
-    always_ff @(posedge clk_host)
-        wr_p1 <= wr;
-
     afifo #(
+        .LGFIFO(6), // use at least 6 to get inferred into BRAM. Increase in ALMs at lower depths
         .WIDTH(2 + REG_FILE_DATA_WIDTH) // address + data
     ) afifo (
 		.i_wclk(clk_host),
 		.i_wr_reset_n(ic_n),
-		.i_wr(wr && !wr_p1), // edge detect if write is held for more than 1 cycle
+		.i_wr(wr), // edge detect if write is held for more than 1 cycle
 		.i_wr_data({address, din}),
 		.o_wr_full(),
 		.i_rclk(clk),

fpga/modules/opl3_fpga_2_0/src/opl3_fpga_v2_0.sv

@@ -77,6 +77,7 @@ module opl3_fpga_v2_0 #(
 	opl3 opl3 (
         .clk(clk_12),
         .clk_host(s_axi_aclk),
+        .clk_dac(1'b0), // unused as we drive DAC clk ourselves using clk_12
         .ic_n(s_axi_aresetn), // clk_host reset
        .*
     );

fpga/modules/top_level/pkg/opl3_pkg.sv

@@ -53,7 +53,7 @@ package opl3_pkg;
     localparam DAC_OUTPUT_WIDTH = 24;
     localparam INSTANTIATE_TIMERS = 1; // set to 1 to use timers, 0 to save area
     localparam NUM_LEDS = 4; // connected to kon bank 0 starting at 0
-    localparam INSTANTIATE_SAMPLE_SYNC_TO_CPU_CLK = 0;
+    localparam INSTANTIATE_SAMPLE_SYNC_TO_DAC_CLK = 0;
 
     localparam DESIRED_SAMPLE_FREQ = 49.7159e3;
     localparam int CLK_DIV_COUNT = $ceil(CLK_FREQ/DESIRED_SAMPLE_FREQ); // unsupported by Quartus 17, set manually

fpga/modules/top_level/src/opl3.sv

@@ -46,6 +46,7 @@ module opl3
 (
     input wire clk, // opl3 clk
     input wire clk_host,
+    input wire clk_dac,
     input wire ic_n, // clk_host reset
     input wire cs_n,
     input wire rd_n,