freecores · cscott111 · Jun 21, 2022
diff --git a/rtl/verilog/i2c_master_bit_ctrl.v b/rtl/verilog/i2c_master_bit_ctrl.v
@@ -135,6 +135,7 @@
 //
 
 `include "i2c_master_defines.v"
+`default_nettype wire   //do not allow undeclared wires
 
 module i2c_master_bit_ctrl (
     input             clk,      // system clock

diff --git a/rtl/verilog/i2c_master_byte_ctrl.v b/rtl/verilog/i2c_master_byte_ctrl.v
@@ -67,6 +67,7 @@
 //
 
 `include "i2c_master_defines.v"
+`default_nettype wire   //do not allow undeclared wires
 
 module i2c_master_byte_ctrl
   (

diff --git a/rtl/verilog/i2c_master_top.v b/rtl/verilog/i2c_master_top.v
@@ -70,6 +70,7 @@
 //
 
 `include "i2c_master_defines.v"
+`default_nettype wire   //do not allow undeclared wires
 
 module i2c_master_top
   (