Run pre-commit

hls4ml/backends/__init__.py

@@ -2,16 +2,20 @@
 from hls4ml.backends.fpga.fpga_backend import FPGABackend  # noqa: F401
 from hls4ml.backends.quartus.quartus_backend import QuartusBackend
 from hls4ml.backends.symbolic.symbolic_backend import SymbolicExpressionBackend
-
+from hls4ml.backends.vitis_accelerator_ip_flow.vitis_accelerator_ip_flow_config import (  # noqa: F401
+    VitisAcceleratorIPFlowConfig,
+)
 from hls4ml.backends.vivado.vivado_backend import VivadoBackend
 from hls4ml.backends.vivado_accelerator.vivado_accelerator_backend import VivadoAcceleratorBackend
 from hls4ml.backends.vivado_accelerator.vivado_accelerator_config import VivadoAcceleratorConfig  # noqa: F401
 
+from hls4ml.backends.vitis_accelerator_ip_flow.vitis_accelerator_ip_flow_backend import (  # isort: skip
+    VitisAcceleratorIPFlowBackend,
+)
+
 from hls4ml.backends.catapult.catapult_backend import CatapultBackend  # isort: skip
 
 from hls4ml.backends.vitis.vitis_backend import VitisBackend  # isort: skip
-from hls4ml.backends.vitis_accelerator_ip_flow.vitis_accelerator_ip_flow_backend import VitisAcceleratorIPFlowBackend  # isort: skip
-from hls4ml.backends.vitis_accelerator_ip_flow.vitis_accelerator_ip_flow_config import VitisAcceleratorIPFlowConfig  # noqa: F401
 
 register_backend('Vivado', VivadoBackend)
 register_backend('VivadoAccelerator', VivadoAcceleratorBackend)

hls4ml/backends/vitis_accelerator_ip_flow/vitis_accelerator_ip_flow_backend.py

@@ -37,22 +37,19 @@ def build(
             # fifo_opt=fifo_opt,
         )
         # Get Config to view Board and Platform
-        from hls4ml.backends import VitisAcceleratorIPFlowConfig
+        # from hls4ml.backends import VitisAcceleratorIPFlowConfig
 
-        vitis_accelerator_ip_flow_config = VitisAcceleratorIPFlowConfig(
-            model.config, model.get_input_variables(), model.get_output_variables()
-        )
+        # vitis_accelerator_ip_flow_config = VitisAcceleratorIPFlowConfig(
+        #     model.config, model.get_input_variables(), model.get_output_variables()
+        # )
         # now make a bitfile
         if bitfile:
-            # if vitis_accelerator_config.get_board().startswith('alveo'):
-            #     self.make_xclbin(model, vitis_accelerator_config.get_platform())
-            # else:
             curr_dir = os.getcwd()
             os.chdir(model.config.get_output_dir())
             try:
-                os.system('vivado -mode batch -source design.tcl') # check if this is accepted as a command
+                os.system('vivado -mode batch -source design.tcl')  # check if this is accepted as a command
             except Exception:
-                print("Something went wrong, check the Vivado logs") 
+                print("Something went wrong, check the Vivado logs")
             os.chdir(curr_dir)
 
         return parse_vivado_report(model.config.get_output_dir())

hls4ml/backends/vitis_accelerator_ip_flow/vitis_accelerator_ip_flow_config.py

@@ -133,7 +133,14 @@ def get_driver_path(self):
         if self.board.startswith('alveo'):
             return '../templates/vitis_accelerator_ip_flow/' + 'alveo/' + self.driver + '_drivers/' + self.get_driver_file()
         else:
-            return '../templates/vitis_accelerator_ip_flow/' + self.board + '/' + self.driver + '_drivers/' + self.get_driver_file()
+            return (
+                '../templates/vitis_accelerator_ip_flow/'
+                + self.board
+                + '/'
+                + self.driver
+                + '_drivers/'
+                + self.get_driver_file()
+            )
 
     def get_driver_file(self):
         driver_ext = '.py' if self.driver == 'python' else '.h'

hls4ml/templates/vitis_accelerator_ip_flow/myproject_axi.cpp

@@ -1,6 +1,6 @@
 // hls-fpga-machine-learning insert include
 
-void myproject_axi(hls::stream< my_pkt > &in, hls::stream< my_pkt > &out) {
+void myproject_axi(hls::stream<my_pkt> &in, hls::stream<my_pkt> &out) {
 
     // hls-fpga-machine-learning insert interface
 

hls4ml/templates/vitis_accelerator_ip_flow/myproject_axi.h

@@ -6,5 +6,5 @@
 
 // hls-fpga-machine-learning insert definitions
 
-void myproject_axi(hls::stream< my_pkt > &in, hls::stream< my_pkt > &out);
+void myproject_axi(hls::stream<my_pkt> &in, hls::stream<my_pkt> &out);
 #endif

hls4ml/templates/vitis_accelerator_ip_flow/zcu102/python_drivers/axi_stream_driver.py

@@ -1,40 +1,38 @@
-from pynq import DefaultHierarchy, DefaultIP, allocate
-from pynq import Overlay
 from datetime import datetime
-import pynq.lib.dma
+
 import numpy as np
-from pynq import PL
+from pynq import PL, Overlay, allocate
 
 
 class NeuralNetworkOverlay(Overlay):
     def __init__(self, bitfile_name, dtbo=None, download=True, ignore_version=False, device=None):
         super().__init__(bitfile_name, dtbo=None, download=True, ignore_version=False, device=None)
-    
+
     def _print_dt(self, timea, timeb, N):
-        dt = (timeb - timea) 
+        dt = timeb - timea
         dts = dt.seconds + dt.microseconds * 10**-6
         rate = N / dts
-        print("Classified {} samples in {} seconds ({} inferences / s)".format(N, dts, rate))
+        print(f"Classified {N} samples in {dts} seconds ({rate} inferences / s)")
         return dts, rate
-    
+
     def reset_PL():
         PL.reset()
-        
+
     def predict(self, X, y_shape, dtype=np.float32, debug=None, profile=False, encode=None, decode=None):
         """
         Obtain the predictions of the NN implemented in the FPGA.
         Parameters:
         - X : the input vector. Should be numpy ndarray.
         - y_shape : the shape of the output vector. Needed to the accelerator to set the TLAST bit properly and
                     for sizing the output vector shape.
-        - dtype : the data type of the elements of the input/output vectors. 
-                  Note: it should be set depending on the interface of the accelerator; if it uses 'float' 
-                  types for the 'data' AXI-Stream field, 'np.float32' dtype is the correct one to use. 
+        - dtype : the data type of the elements of the input/output vectors.
+                  Note: it should be set depending on the interface of the accelerator; if it uses 'float'
+                  types for the 'data' AXI-Stream field, 'np.float32' dtype is the correct one to use.
                   Instead if it uses 'ap_fixed<A,B>', 'np.intA' is the correct one to use (note that A cannot
-                  any integer value, but it can assume {..., 8, 16, 32, ...} values. Check `numpy` 
+                  any integer value, but it can assume {..., 8, 16, 32, ...} values. Check `numpy`
                   doc for more info).
-                  In this case the encoding/decoding has to be computed by the PS. For example for 
-                  'ap_fixed<16,6>' type the following 2 functions are the correct one to use for encode/decode 
+                  In this case the encoding/decoding has to be computed by the PS. For example for
+                  'ap_fixed<16,6>' type the following 2 functions are the correct one to use for encode/decode
                   'float' -> 'ap_fixed<16,6>':
                   ```
                     def encode(xi):
@@ -52,13 +50,12 @@ def decode(yi):
 
         if encode is not None:
             X = encode(X)
-        with allocate(shape=X.shape, dtype=dtype) as input_buffer, \
-             allocate(shape=y_shape, dtype=dtype) as output_buffer:
+        with allocate(shape=X.shape, dtype=dtype) as input_buffer, allocate(shape=y_shape, dtype=dtype) as output_buffer:
             input_buffer[:] = X
-            
+
             if profile:
                 timea = datetime.now()
-            
+
             self.axi_dma_0.sendchannel.transfer(input_buffer)
             self.axi_dma_0.recvchannel.transfer(output_buffer)
             if debug:
@@ -67,20 +64,20 @@ def decode(yi):
             if debug:
                 print("Send OK")
             self.axi_dma_0.recvchannel.wait()
-            
+
             if profile:
                 timeb = datetime.now()
-            
+
             if debug:
                 print("Receive OK")
-              
+
             result = output_buffer.copy()
-            
+
         if decode is not None:
             result = decode(result)
-            
+
         if profile:
             dts, rate = self._print_dt(timea, timeb, len(X))
             return result, dts, rate
 
-        return result
+        return result

hls4ml/templates/vivado/nnet_utils/nnet_helpers.h

@@ -167,16 +167,18 @@ template <class srcType, class dstType, size_t SIZE> void convert_data(hls::stre
 }
 
 #ifdef VITIS_ACCELERATOR_IP_FLOW
-//todo avoid hardcoding hls::axis<float, 0, 0, 0> and use template
-template <class srcType, typename dstType, size_t SIZE> void convert_data(srcType *src, hls::stream<hls::axis<float, 0, 0, 0>> &dst) {
+// todo avoid hardcoding hls::axis<float, 0, 0, 0> and use template
+template <class srcType, typename dstType, size_t SIZE>
+void convert_data(srcType *src, hls::stream<hls::axis<float, 0, 0, 0>> &dst) {
     for (size_t i = 0; i < SIZE; i++) {
         hls::axis<float, 0, 0, 0> ctype;
         ctype.data = dstType(src[i]);
         dst.write(ctype);
     }
 }
 
-template <typename srcType, class dstType, size_t SIZE> void convert_data(hls::stream<hls::axis<float, 0, 0, 0>> &src, dstType *dst) {
+template <typename srcType, class dstType, size_t SIZE>
+void convert_data(hls::stream<hls::axis<float, 0, 0, 0>> &src, dstType *dst) {
     for (size_t i = 0; i < SIZE; i++) {
         hls::axis<float, 0, 0, 0> ctype = src.read();
         dst[i] = dstType(ctype.data);
@@ -323,8 +325,7 @@ template <class res_T, size_t SIZE> void print_result(res_T result[SIZE], std::o
     out << std::endl;
 }
 
-template <class res_T, size_t SIZE,
-          typename std::enable_if<std::is_array<res_T>::value, int>::type = 0>
+template <class res_T, size_t SIZE, typename std::enable_if<std::is_array<res_T>::value, int>::type = 0>
 void print_result(hls::stream<res_T> &result, std::ostream &out, bool keep = false) {
     for (int i = 0; i < SIZE / res_T::size; i++) {
         res_T res_pack = result.read();
@@ -333,46 +334,45 @@ void print_result(hls::stream<res_T> &result, std::ostream &out, bool keep = fal
         }
         if (keep) {
             result.write(res_pack);
-        }           
+        }
     }
     out << std::endl;
 }
 
 // compatible with Vitis Accelerator for res_T = hls::axis<...> and io_parallel
-template <class res_T, size_t SIZE,
-          typename std::enable_if<!std::is_array<res_T>::value, int>::type = 0>
+template <class res_T, size_t SIZE, typename std::enable_if<!std::is_array<res_T>::value, int>::type = 0>
 void print_result(hls::stream<res_T> &result, std::ostream &out, bool keep = false) {
     for (int i = 0; i < SIZE; i++) {
         res_T res_pack = result.read();
-        
+
         out << res_pack.data << " ";
-        
+
         if (keep) {
             result.write(res_pack);
-        }           
+        }
     }
     out << std::endl;
 }
 
 // compatible with Vitis Accelerator for res_T = hls::axis<underlying_data_T, ...> and io_stream
-template <class underlying_res_T, class res_T, size_t SIZE> void print_result(hls::stream<res_T> &result, std::ostream &out, bool keep = false) {
+template <class underlying_res_T, class res_T, size_t SIZE>
+void print_result(hls::stream<res_T> &result, std::ostream &out, bool keep = false) {
     for (int i = 0; i < SIZE / underlying_res_T::size; i++) {
         res_T res_pack;
         for (int j = 0; j < underlying_res_T::size; j++) {
             res_pack = result.read();
             out << res_pack.data << " ";
             if (keep) {
                 result.write(res_pack);
-            }   
-        }        
+            }
+        }
     }
     out << std::endl;
 }
 
 template <class data_T, size_t SIZE> void fill_zero(data_T data[SIZE]) { std::fill_n(data, SIZE, 0.); }
 
-template <class data_T, size_t SIZE,
-          typename std::enable_if<std::is_array<data_T>::value, int>::type = 0>
+template <class data_T, size_t SIZE, typename std::enable_if<std::is_array<data_T>::value, int>::type = 0>
 void fill_zero(hls::stream<data_T> &data) {
     for (int i = 0; i < SIZE / data_T::size; i++) {
         data_T data_pack;
@@ -383,16 +383,14 @@ void fill_zero(hls::stream<data_T> &data) {
     }
 }
 
-template <class data_T, size_t SIZE,
-          typename std::enable_if<!std::is_array<data_T>::value, int>::type = 0>
+template <class data_T, size_t SIZE, typename std::enable_if<!std::is_array<data_T>::value, int>::type = 0>
 void fill_zero(hls::stream<data_T> &data) {
     for (int i = 0; i < SIZE; i++) {
         data_T data_pack;
         data_pack.data = 0.;
-        if (i==SIZE-1) {
+        if (i == SIZE - 1) {
             data_pack.last = 1;
-        }
-        else {
+        } else {
             data_pack.last = 0;
         }
         data.write(data_pack);
@@ -405,15 +403,13 @@ template <class underlying_data_T, class data_T, size_t SIZE> void fill_zero(hls
         data_T data_pack;
         for (int j = 0; j < underlying_data_T::size; j++) {
             data_pack.data = 0.;
-            if ((i==(SIZE / underlying_data_T::size-1)) && (j==(underlying_data_T::size-1))) {
+            if ((i == (SIZE / underlying_data_T::size - 1)) && (j == (underlying_data_T::size - 1))) {
                 data_pack.last = 1;
-            }
-            else {
+            } else {
                 data_pack.last = 0;
             }
             data.write(data_pack);
         }
-
     }
 }
 

hls4ml/writer/__init__.py

@@ -1,8 +1,8 @@
 from hls4ml.writer.catapult_writer import CatapultWriter
 from hls4ml.writer.quartus_writer import QuartusWriter
 from hls4ml.writer.symbolic_writer import SymbolicExpressionWriter
-from hls4ml.writer.vitis_writer import VitisWriter
 from hls4ml.writer.vitis_accelerator_ip_flow_writer import VitisAcceleratorIPFlowWriter
+from hls4ml.writer.vitis_writer import VitisWriter
 from hls4ml.writer.vivado_accelerator_writer import VivadoAcceleratorWriter
 from hls4ml.writer.vivado_writer import VivadoWriter
 from hls4ml.writer.writers import Writer, get_writer, register_writer  # noqa: F401