soc/cores/video/VideoFramebuffer: Add VTG/DMA synchronization when DM…

…A is enabled to simplify use.
enjoy-digital · Oct 6, 2023 · cd82187 · cd82187
1 parent 98eb27d
commit cd82187
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Showing 2 changed files with 21 additions and 3 deletions.
diff --git a/CHANGES.md b/CHANGES.md
@@ -9,6 +9,7 @@
 	cpu/neorv32       : Added Debug support and update core complex.
 	cpu/vexriscv_smp  : Added hardware breakpoints support.
 	build/colognechip : Added initial support.
+	soc/cores/video   : Added VTG/DMA synchronization stage to VideoFramebuffer.
 
 	[> Changed
 	----------

diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py
@@ -692,16 +692,33 @@ def __init__(self, dram_port, hres=800, vres=600, base=0x00000000, fifo_depth=65
                 ]
             video_pipe_source = self.cdc.source
 
-        # Video Generation.
-        self.comb += [
+        # Video Synchronization/Generation.
+        fsm = FSM(reset_state="VTG-SYNC")
+        fsm = ClockDomainsRenamer(clock_domain)(fsm)
+        fsm = ResetInserter()(fsm)
+        self.submodules += fsm
+        self.specials += MultiReg(self.dma.fsm.reset, fsm.reset, clock_domain)
+        fsm.act("VTG-SYNC",
+            vtg_sink.ready.eq(1),
+            If(vtg_sink.valid & vtg_sink.last,
+                NextState("DMA-SYNC")
+            )
+        )
+        fsm.act("DMA-SYNC",
+            video_pipe_source.ready.eq(1),
+            If(video_pipe_source.valid & video_pipe_source.last,
+                NextState("RUN")
+            )
+        )
+        fsm.act("RUN",
             vtg_sink.ready.eq(1),
             If(vtg_sink.valid & vtg_sink.de,
                 video_pipe_source.connect(source, keep={"valid", "ready"}),
                 vtg_sink.ready.eq(source.valid & source.ready),
 
             ),
             vtg_sink.connect(source, keep={"de", "hsync", "vsync"}),
-        ]
+        )
         if (depth == 32):
             self.comb += [
                source.r.eq(video_pipe_source.data[ 0: 8]),