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Merge branch 'enjoy-digital:master' into master
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@John-Tito
John-Tito authored Nov 9, 2024
2 parents f47d094 + 8b4949e commit 9f7186a
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Showing 2 changed files with 118 additions and 101 deletions.
217 changes: 117 additions & 100 deletions litex/soc/cores/cpu/urv/core.py
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,102 @@
"standard": "-march=rv32i2p0_m -mabi=ilp32",
}

# uRV ------------------------------------------------------------------------------------------
# uRV Instruction Bus To Wishbone ------------------------------------------------------------------

instruction_bus_layout = [
("addr", 32),
("rd", 1),
("data", 32),
("valid", 1)
]

class InstructionBusToWishbone(LiteXModule):
def __init__(self, ibus, wb_ibus):
self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(ibus.rd,
NextValue(ibus.valid, 0),
NextState("READ")
)
)
fsm.act("READ",
wb_ibus.stb.eq(1),
wb_ibus.cyc.eq(1),
wb_ibus.we.eq(0),
wb_ibus.adr.eq(ibus.addr),
wb_ibus.sel.eq(0b1111),
If(wb_ibus.ack,
NextValue(ibus.valid, 1),
NextValue(ibus.data, wb_ibus.dat_r),
NextState("IDLE")
)
)

# uRV Data Bus To Wishbone -------------------------------------------------------------------------

data_bus_layout = [
("addr", 32),
("data_s", 32),
("data_l", 32),
("sel", 4),
("store", 1),
("load", 1),
("load_done", 1),
("store_done", 1)
]

class DataBusToWishbone(LiteXModule):
def __init__(self, dbus, wb_dbus):
self.fifo = fifo = stream.SyncFIFO(
layout=[("addr", 32), ("we", 1), ("data", 32), ("sel", 4)],
depth=16,
)
self.comb += [
fifo.sink.valid.eq(dbus.store | dbus.load),
fifo.sink.we.eq(dbus.store),
fifo.sink.addr.eq(dbus.addr),
fifo.sink.data.eq(dbus.data_s),
fifo.sink.sel.eq(dbus.sel),
]

self.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(fifo.source.valid,
If(fifo.source.we,
NextState("WRITE")
).Else(
NextState("READ")
)
)
)
fsm.act("WRITE",
wb_dbus.stb.eq(1),
wb_dbus.cyc.eq(1),
wb_dbus.we.eq(1),
wb_dbus.adr.eq(fifo.source.addr),
wb_dbus.sel.eq(fifo.source.sel),
wb_dbus.dat_w.eq(fifo.source.data),
If(wb_dbus.ack,
fifo.source.ready.eq(1),
dbus.store_done.eq(1),
NextState("IDLE")
)
)
fsm.act("READ",
wb_dbus.stb.eq(1),
wb_dbus.cyc.eq(1),
wb_dbus.we.eq(0),
wb_dbus.adr.eq(fifo.source.addr),
wb_dbus.sel.eq(fifo.source.sel),
If(wb_dbus.ack,
fifo.source.ready.eq(1),
dbus.load_done.eq(1),
dbus.data_l.eq(wb_dbus.dat_r),
NextState("IDLE")
)
)

# uRV ----------------------------------------------------------------------------------------------

class uRV(CPU):
category = "softcore"
Expand Down Expand Up @@ -66,21 +161,10 @@ def __init__(self, platform, variant="standard"):
self.periph_buses = [ibus, dbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).

# uRV Signals.
# ------------
im_addr = Signal(32)
im_rd = Signal()
im_data = Signal(32)
im_valid = Signal()

dm_addr = Signal(32)
dm_data_s = Signal(32)
dm_data_l = Signal(32)
dm_data_select = Signal(4)
dm_store = Signal()
dm_load = Signal()
dm_load_done = Signal()
dm_store_done = Signal()
# uRV Buses.
# ----------
im_bus = Record(instruction_bus_layout)
dm_bus = Record(data_bus_layout)

# uRV Instance.
# -------------
Expand All @@ -100,94 +184,27 @@ def __init__(self, platform, variant="standard"):
i_rst_i = ResetSignal("sys") | self.reset,

# Instruction Mem Bus.
o_im_addr_o = im_addr,
o_im_rd_o = im_rd,
i_im_data_i = im_data,
i_im_valid_i = im_valid,
o_im_addr_o = im_bus.addr,
o_im_rd_o = im_bus.rd,
i_im_data_i = im_bus.data,
i_im_valid_i = im_bus.valid,

# Data Mem Bus.
o_dm_addr_o = dm_addr,
o_dm_data_s_o = dm_data_s,
i_dm_data_l_i = dm_data_l,
o_dm_data_select_o = dm_data_select,

o_dm_store_o = dm_store,
o_dm_load_o = dm_load,
i_dm_load_done_i = dm_load_done,
i_dm_store_done_i = dm_store_done,
o_dm_addr_o = dm_bus.addr,
o_dm_data_s_o = dm_bus.data_s,
i_dm_data_l_i = dm_bus.data_l,
o_dm_data_select_o = dm_bus.sel,

o_dm_store_o = dm_bus.store,
o_dm_load_o = dm_bus.load,
i_dm_load_done_i = dm_bus.load_done,
i_dm_store_done_i = dm_bus.store_done,
)

# uRV Instruction Bus.
# --------------------
self.i_fsm = i_fsm = FSM(reset_state="IDLE")
i_fsm.act("IDLE",
If(im_rd,
NextValue(im_valid, 0),
NextState("READ")
)
)
i_fsm.act("READ",
ibus.stb.eq(1),
ibus.cyc.eq(1),
ibus.we.eq(0),
ibus.adr.eq(im_addr),
ibus.sel.eq(0b1111),
If(ibus.ack,
NextValue(im_valid, 1),
NextValue(im_data, ibus.dat_r),
NextState("IDLE")
)
)

# uRV Data Bus.
# -------------
self.dm_fifo = dm_fifo = stream.SyncFIFO(
layout = [("addr", 32), ("we", 1), ("data", 32), ("sel", 4)],
depth = 16,
)
self.comb += [
dm_fifo.sink.valid.eq(dm_store | dm_load),
dm_fifo.sink.we.eq(dm_store),
dm_fifo.sink.addr.eq(dm_addr),
dm_fifo.sink.data.eq(dm_data_s),
dm_fifo.sink.sel.eq(dm_data_select),
]
self.dm_fsm = dm_fsm = FSM(reset_state="IDLE")
dm_fsm.act("IDLE",
If(dm_fifo.source.valid,
If(dm_fifo.source.we,
NextState("WRITE")
).Else(
NextState("READ")
)
)
)
dm_fsm.act("WRITE",
dbus.stb.eq(1),
dbus.cyc.eq(1),
dbus.we.eq(1),
dbus.adr.eq(dm_fifo.source.addr),
dbus.sel.eq(dm_fifo.source.sel),
dbus.dat_w.eq(dm_fifo.source.data),
If(dbus.ack,
dm_fifo.source.ready.eq(1),
dm_store_done.eq(1),
NextState("IDLE")
)
)
dm_fsm.act("READ",
dbus.stb.eq(1),
dbus.cyc.eq(1),
dbus.we.eq(0),
dbus.adr.eq(dm_fifo.source.addr),
dbus.sel.eq(dm_fifo.source.sel),
If(dbus.ack,
dm_fifo.source.ready.eq(1),
dm_load_done.eq(1),
dm_data_l.eq(dbus.dat_r),
NextState("IDLE")
)
)
# uRV Bus Adaptation.
# -------------------
self.submodules += InstructionBusToWishbone(im_bus, ibus)
self.submodules += DataBusToWishbone(dm_bus, dbus)

# Add Verilog sources.
# --------------------
Expand Down
2 changes: 1 addition & 1 deletion litex/soc/integration/soc.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,7 @@ def check_region_is_in(self, region, container):
is_in = True
if not (region.origin >= container.origin):
is_in = False
if not ((region.origin + region.size) < (container.origin + container.size)):
if not ((region.origin + region.size) <= (container.origin + container.size)):
is_in = False
return is_in

Expand Down

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