all gpu kernels compiling on CPU and GPU!

emer · Nov 2, 2024 · 99e08a4 · 99e08a4
1 parent c863b80
commit 99e08a4
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Showing 4 changed files with 4 additions and 6 deletions.
diff --git a/axon/network.go b/axon/network.go
diff --git a/axon/network.goal b/axon/network.goal
@@ -382,7 +382,7 @@ func DWtSyn(i uint32) { //gosl:kernel
 	pti := SynapseIxs[SynPathIndex, syni]
 	si := SynapseIxs[SynSendIndex, syni]
 	ri := SynapseIxs[SynRecvIndex, syni]
-	Paths[pti].DWtSyn(ctx, syni, si, ri, di)
+	Paths[pti].DWtSyn(ctx, &Layers[Paths[pti].Indexes.RecvLayer], syni, si, ri, di)
 }
 
 // DWtFromDiSyn is the kernel over Synapses (not * Data) to

diff --git a/axon/pathparams.go b/axon/pathparams.go
diff --git a/axon/pathparams.goal b/axon/pathparams.goal
@@ -346,11 +346,10 @@ func (pt *PathParams) SendSpike(ctx *Context, ni, di, lni uint32) {
 // DWtSyn is the overall entry point for weight change (learning) at given synapse.
 // It selects appropriate function based on pathway type.
 // rpl is the receiving layer SubPool
-func (pt *PathParams) DWtSyn(ctx *Context, syni, si, ri, di uint32) {
+func (pt *PathParams) DWtSyn(ctx *Context, rlay *LayerParams, syni, si, ri, di uint32) {
 	if pt.Learn.Learn == 0 {
 		return
 	}
-	rlay := &Layers[pt.Indexes.RecvLayer]
 	isTarget := rlay.Acts.Clamp.IsTarget > 0
 	spi := NeuronIxs[NrnSubPool, ri]
 	pi := rlay.PoolIndex(spi)