update for Cortex-A9.

ports/cortex_a7/gnu/example_build/MP_PrivateTimer.S

@@ -0,0 +1,85 @@
+// ------------------------------------------------------------
+// Cortex-A MPCore - Private timer functions
+//
+// Copyright ARM Ltd 2009. All rights reserved.
+// ------------------------------------------------------------
+
+  .text
+  .align 3
+
+  // PPI ID 29
+
+
+  // Typical set of calls to enable Timer:
+  // init_private_timer(0xXXXX, 0)   <-- Counter down value of 0xXXXX, with auto-reload
+  // start_private_timer()
+
+  // Timer offset from base of private peripheral space --> 0x600
+
+// ------------------------------------------------------------
+
+  .global init_private_timer
+  .type init_private_timer,function
+  // void init_private_timer(unsigned int load_value, unsigned int auto_reload)
+  // Sets up the private timer
+  // r0: initial load value
+  // r1:  IF 0 (AutoReload) ELSE (SingleShot)
+init_private_timer:
+
+  // Setup timeout value (CNTP_TVAL)
+  MCR     p15, 0, r0, c14, c2, 0
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // void start_private_timer(void)
+  // Starts the private timer
+  .global start_private_timer
+  .type start_private_timer,function
+start_private_timer:
+
+  MOV     r0, #0x1
+
+  // Enable timer (CNTP_CTL)
+  MCR     p15, 0, r0, c14, c2, 1
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // void stop_private_timer(void)
+  // Stops the private timer
+  .global stop_private_timer
+  .type stop_private_timer,function
+stop_private_timer:
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // unsigned int read_private_timer(void)
+  // Reads the current value of the timer count register
+  .global get_private_timer_count
+  .type get_private_timer_count,function
+get_private_timer_count:
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // void clear_private_timer_irq(void)
+  // Clears the private timer interrupt
+  .global clear_private_timer_irq
+  .type clear_private_timer_irq,function
+clear_private_timer_irq:
+
+  BX      lr
+
+// ------------------------------------------------------------
+// End of code
+// ------------------------------------------------------------
+
+// ------------------------------------------------------------
+// End of MP_PrivateTimer.s
+// ------------------------------------------------------------

ports/cortex_a7/gnu/example_build/MP_PrivateTimer.h

@@ -0,0 +1,36 @@
+// ------------------------------------------------------------
+// Cortex-A MPCore - Private timer functions
+// Header Filer
+//
+// Copyright ARM Ltd 2009. All rights reserved.
+// ------------------------------------------------------------
+
+#ifndef _CORTEXA_PRIVATE_TIMER_
+#define _CORTEXA_PRIVATE_TIMER_
+
+// Typical set of calls to enable Timer:
+// init_private_timer(0xXXXX, 0)   <-- Counter down value of 0xXXXX, with auto-reload
+// start_private_timer()
+
+// Sets up the private timer
+// r0: initial load value
+// r1:  IF 0 (AutoReload) ELSE (SingleShot)
+void init_private_timer(unsigned int load_value, unsigned int auto_reload);
+
+// Starts the private timer
+void start_private_timer(void);
+
+// Stops the private timer
+void stop_private_timer(void);
+
+// Reads the current value of the timer count register
+unsigned int get_private_timer_count(void);
+
+// Clears the private timer interrupt
+void clear_private_timer_irq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of MP_PrivateTimer.h
+// ------------------------------------------------------------

ports/cortex_a7/gnu/example_build/build_threadx_sample.bat

@@ -2,9 +2,7 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-a7 reset.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 crt0.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 tx_initialize_low_level.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 MP_GIC.s
+arm-none-eabi-gcc -c -g -mcpu=cortex-a7 MP_PrivateTimer.s
 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 V7.s
 arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc sample_threadx.c
-arm-none-eabi-gcc -g -nostartfiles -mcpu=cortex-a7 -T sample_threadx.ld --specs=nosys.specs -o sample_threadx.out -Wl,-Map=sample_threadx.map MP_GIC.o V7.o crt0.o reset.o tx_initialize_low_level.o sample_threadx.o tx.a
-
-
-
+arm-none-eabi-gcc -g -nostartfiles -mcpu=cortex-a7 -T sample_threadx.ld --specs=nosys.specs -o sample_threadx.out -Wl,-Map=sample_threadx.map MP_GIC.o MP_PrivateTimer.o V7.o crt0.o reset.o tx_initialize_low_level.o sample_threadx.o tx.a

ports/cortex_a7/gnu/example_build/tx_initialize_low_level.S

@@ -41,8 +41,13 @@ SYS_STACK_SIZE  =       1024                    // System stack size
     .global     _end
     .global     _sp
     .global     _stack_bottom
-
-
+    .global     __vectors
+    .global     disableHighVecs
+    .global     enableGIC
+    .global     enableGICProcessorInterface
+    .global     enableCaches
+    .global     init_private_timer
+    .global     start_private_timer
 /* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for
    applications calling this function from to 16-bit Thumb mode.  */
 
@@ -160,6 +165,57 @@ _stack_error_loop:
     ADD     r1, r1, #8                          // Increment to next free word
     STR     r1, [r2]                            // Save first free memory address
 
+    PUSH    {lr}
+
+    /* Setup the vector table.  */
+    LDR     r0, =__vectors                      // Get address of vector table
+    MCR     p15, 0, r0, c12, c0, 0              // Write vector table address to CP15
+    BL      disableHighVecs                     // Disable high vectors
+
+    //
+    // GIC Init
+    // ---------
+    BL      enableGIC
+    BL      enableGICProcessorInterface
+
+    //
+    // Enable Private Timer for periodic IRQ
+    // --------------------------------------
+    MOV     r0, #0x1F
+    BL      setPriorityMask               // Set priority mask (local)
+
+    // [EL] Change start - don't enable interrupts here!  
+    //CPSIE   i                            // Clear CPSR I bit
+    // [EL] Change end
+
+    // Enable the Private Timer Interrupt Source
+    MOV     r0, #29
+    MOV     r1, #0
+    BL      enableIntID
+
+    // Set the priority
+    MOV     r0, #29
+    MOV     r1, #0
+    BL      setIntPriority
+
+    // Configure Timer
+    MOV     r0, #0xF0000
+    MOV     r1, #0x0
+    BL      init_private_timer
+    BL      start_private_timer
+
+    //
+    // Enable receipt of SGI 0
+    // ------------------------
+    MOV     r0, #0x0                  // ID
+    BL      enableIntID
+
+    // Set the priority
+    MOV     r0, #0x0                  // ID
+    MOV     r1, #0x0                  // Priority
+    BL      setIntPriority
+
+    POP    {lr}
 #ifdef __THUMB_INTERWORK
     BX      lr                                  // Return to caller
 #else
@@ -202,30 +258,29 @@ __tx_irq_processing_return:
        if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
        small code sequences where lr is saved before enabling interrupts and
        restored after interrupts are again disabled.  */
+
+    PUSH    {r4, r5}            // Save some preserved registers (r5 is saved just for 8-byte alignment)
+    BL      readIntAck
+    MOV     r4, r0
 
-    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
-       from IRQ mode with interrupts disabled.  This routine switches to the
-       system mode and returns with IRQ interrupts enabled.
+    CMP     r0, #29             // If not Private Timer interrupt (ID 29), by pass
+    BNE     by_pass_timer_interrupt
 
-       NOTE:  It is very important to ensure all IRQ interrupts are cleared
-       prior to enabling nested IRQ interrupts.  */
-#ifdef TX_ENABLE_IRQ_NESTING
-    BL      _tx_thread_irq_nesting_start
-#endif
+    MOV     r0, #0xF0000
+    MOV     r1, #0x0
+    BL      init_private_timer
+    DSB
 
     /* For debug purpose, execute the timer interrupt processing here.  In
        a real system, some kind of status indication would have to be checked
        before the timer interrupt handler could be called.  */
 
     BL     _tx_timer_interrupt                  // Timer interrupt handler
 
-
-    /* If interrupt nesting was started earlier, the end of interrupt nesting
-       service must be called before returning to _tx_thread_context_restore.
-       This routine returns in processing in IRQ mode with interrupts disabled.  */
-#ifdef TX_ENABLE_IRQ_NESTING
-    BL      _tx_thread_irq_nesting_end
-#endif
+by_pass_timer_interrupt:
+    MOV     r0, r4
+    BL      writeEOI
+    POP     {r4, r5}                            // Recover preserved registers
 
     /* Jump to context restore to restore system context.  */
     B       _tx_thread_context_restore

ports/cortex_a8/gnu/example_build/MP_PrivateTimer.S

@@ -0,0 +1,85 @@
+// ------------------------------------------------------------
+// Cortex-A MPCore - Private timer functions
+//
+// Copyright ARM Ltd 2009. All rights reserved.
+// ------------------------------------------------------------
+
+  .text
+  .align 3
+
+  // PPI ID 29
+
+
+  // Typical set of calls to enable Timer:
+  // init_private_timer(0xXXXX, 0)   <-- Counter down value of 0xXXXX, with auto-reload
+  // start_private_timer()
+
+  // Timer offset from base of private peripheral space --> 0x600
+
+// ------------------------------------------------------------
+
+  .global init_private_timer
+  .type init_private_timer,function
+  // void init_private_timer(unsigned int load_value, unsigned int auto_reload)
+  // Sets up the private timer
+  // r0: initial load value
+  // r1:  IF 0 (AutoReload) ELSE (SingleShot)
+init_private_timer:
+
+  // Setup timeout value (CNTP_TVAL)
+  MCR     p15, 0, r0, c14, c2, 0
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // void start_private_timer(void)
+  // Starts the private timer
+  .global start_private_timer
+  .type start_private_timer,function
+start_private_timer:
+
+  MOV     r0, #0x1
+
+  // Enable timer (CNTP_CTL)
+  MCR     p15, 0, r0, c14, c2, 1
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // void stop_private_timer(void)
+  // Stops the private timer
+  .global stop_private_timer
+  .type stop_private_timer,function
+stop_private_timer:
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // unsigned int read_private_timer(void)
+  // Reads the current value of the timer count register
+  .global get_private_timer_count
+  .type get_private_timer_count,function
+get_private_timer_count:
+
+  BX      lr
+
+// ------------------------------------------------------------
+
+  // void clear_private_timer_irq(void)
+  // Clears the private timer interrupt
+  .global clear_private_timer_irq
+  .type clear_private_timer_irq,function
+clear_private_timer_irq:
+
+  BX      lr
+
+// ------------------------------------------------------------
+// End of code
+// ------------------------------------------------------------
+
+// ------------------------------------------------------------
+// End of MP_PrivateTimer.s
+// ------------------------------------------------------------

ports/cortex_a8/gnu/example_build/MP_PrivateTimer.h

@@ -0,0 +1,36 @@
+// ------------------------------------------------------------
+// Cortex-A MPCore - Private timer functions
+// Header Filer
+//
+// Copyright ARM Ltd 2009. All rights reserved.
+// ------------------------------------------------------------
+
+#ifndef _CORTEXA_PRIVATE_TIMER_
+#define _CORTEXA_PRIVATE_TIMER_
+
+// Typical set of calls to enable Timer:
+// init_private_timer(0xXXXX, 0)   <-- Counter down value of 0xXXXX, with auto-reload
+// start_private_timer()
+
+// Sets up the private timer
+// r0: initial load value
+// r1:  IF 0 (AutoReload) ELSE (SingleShot)
+void init_private_timer(unsigned int load_value, unsigned int auto_reload);
+
+// Starts the private timer
+void start_private_timer(void);
+
+// Stops the private timer
+void stop_private_timer(void);
+
+// Reads the current value of the timer count register
+unsigned int get_private_timer_count(void);
+
+// Clears the private timer interrupt
+void clear_private_timer_irq(void);
+
+#endif
+
+// ------------------------------------------------------------
+// End of MP_PrivateTimer.h
+// ------------------------------------------------------------

ports/cortex_a8/gnu/example_build/build_threadx_sample.bat

@@ -2,7 +2,7 @@ arm-none-eabi-gcc -c -g -mcpu=cortex-a8 reset.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 crt0.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 tx_initialize_low_level.S
 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 MP_GIC.s
+arm-none-eabi-gcc -c -g -mcpu=cortex-a8 MP_PrivateTimer.s
 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 V7.s
 arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc sample_threadx.c
-arm-none-eabi-gcc -g -nostartfiles -mcpu=cortex-a8 -T sample_threadx.ld --specs=nosys.specs -o sample_threadx.out -Wl,-Map=sample_threadx.map MP_GIC.o V7.o crt0.o reset.o tx_initialize_low_level.o sample_threadx.o tx.a
-
+arm-none-eabi-gcc -g -nostartfiles -mcpu=cortex-a8 -T sample_threadx.ld --specs=nosys.specs -o sample_threadx.out -Wl,-Map=sample_threadx.map MP_GIC.o MP_PrivateTimer.o V7.o crt0.o reset.o tx_initialize_low_level.o sample_threadx.o tx.a