Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

SystemVerilog: string data type #838

Draft
wants to merge 2 commits into
base: main
Choose a base branch
from
Draft

SystemVerilog: string data type #838

wants to merge 2 commits into from

Conversation

kroening
Copy link
Member

This adds 1800-2017 6.16 string.

@kroening kroening changed the title SystemVerilog: string data type SystemVerilog: string data type Nov 21, 2024
@kroening kroening force-pushed the verilog_string branch 5 times, most recently from c242045 to b7f5809 Compare December 29, 2024 20:06
This adds 1800-2017 6.17 event.
This adds 1800-2017 6.16 string.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant