Verilog: add KNOWNBUG test for enums in module hierarchy

regression/verilog/enums/enum_with_hierarchy1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+enum_with_hierarchy1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+Asserted values are wrong.

regression/verilog/enums/enum_with_hierarchy1.sv

@@ -0,0 +1,18 @@
+module sub;
+
+  parameter step = 1;
+
+  typedef enum { E0 = 0 * step, E1 = 1 * step, E2 = 2 * step } my_enumt;
+
+endmodule
+
+module main;
+
+  // The value of enum constants may differ for each module instance.
+  sub #(1) sub1();
+  sub #(2) sub2();
+
+  p1: assert property (sub1.E0 == 0 && sub1.E1 == 1 && sub1.E2 == 2);
+  p2: assert property (sub2.E0 == 0 && sub2.E2 == 2 && sub2.E2 == 4);
+
+endmodule