Verilog: add tests for combiations of declarations

regression/verilog/data-types/enum_name_collision.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+enum_name_collision.sv
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The name collision should be errored.

regression/verilog/data-types/enum_name_collision.sv

@@ -0,0 +1,8 @@
+module main;
+
+  typedef enum { some_identifier } some_type;
+
+  // name collision
+  wire some_identifier;
+
+endmodule

regression/verilog/modules/inout_and_reg.desc

@@ -0,0 +1,7 @@
+CORE
+inout_and_reg.v
+
+^file .* line 4: symbol `some_var' is declared both as input and as register$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/modules/inout_and_reg.v

@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be both an input and a reg
+  inout [31:0] some_var;
+  reg [31:0] some_var;
+endmodule

regression/verilog/modules/input_and_ansi_input.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+input_and_ansi_input.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The redeclaration must be errored.

regression/verilog/modules/input_and_ansi_input.v

@@ -0,0 +1,4 @@
+module main(input [31:0] some_var);
+  // some_var must not be redeclared
+  input [31:0] some_var;
+endmodule

regression/verilog/modules/input_and_output.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+input_and_output.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+This should be errored, as some_var must not be both input and output.

regression/verilog/modules/input_and_output.v

@@ -0,0 +1,5 @@
+module main(x);
+  // cannot declare both as input and output
+  input [31:0] x;
+  output [31:0] x;
+endmodule

regression/verilog/modules/input_and_reg.desc

@@ -0,0 +1,7 @@
+CORE
+input_and_reg.v
+
+^file .* line 4: symbol `some_var' is declared both as input and as register$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/modules/input_and_reg.v

@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be both an input and a reg
+  input [31:0] some_var;
+  reg [31:0] some_var;
+endmodule

regression/verilog/modules/parameter_name_collision.desc

@@ -0,0 +1,7 @@
+CORE
+parameter_name_collision.v
+
+^file .* line 4: definition of symbol `p' conflicts with earlier definition at line 3$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/modules/parameter_name_collision.v

@@ -0,0 +1,6 @@
+module main;
+
+  parameter p = 123;
+  parameter p = 123;
+
+endmodule

regression/verilog/modules/wire_and_output.desc

@@ -0,0 +1,7 @@
+CORE
+wire_and_output.v
+--module M1
+^no properties$
+^EXIT=10$
+^SIGNAL=0$
+--

regression/verilog/modules/wire_and_output.v

@@ -0,0 +1,10 @@
+module M1(some_port);
+  output [31:0] some_port;
+  wire [31:0] some_port;
+endmodule
+
+module M2(some_port);
+  // order flipped
+  wire [31:0] some_port;
+  output [31:0] some_port;
+endmodule

regression/verilog/modules/wire_and_reg.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+wire_and_reg.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+This should be errored, as some_var must not be both wire and reg.

regression/verilog/modules/wire_and_reg.v

@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be both wire and reg
+  wire [31:0] some_var;
+  reg [31:0] some_var;
+endmodule

regression/verilog/modules/wire_and_wire.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+input_and_reg.v
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The redeclaration must be errored.

regression/verilog/modules/wire_and_wire.v

@@ -0,0 +1,5 @@
+module main;
+  // some_var must not be redeclared
+  wire [31:0] some_var;
+  wire [31:0] some_var;
+endmodule

regression/verilog/tasks/task_name_collision.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+task_name_collision.v
+
+^definition of symbol `some_task' conflicts with earlier definition at line$
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The line number is missing.

regression/verilog/tasks/task_name_collision.v

@@ -0,0 +1,13 @@
+module main;
+
+  reg [31:0] data;
+
+  task some_task;
+    data = 123;
+  endtask
+
+  task some_task;
+    data = 456;
+  endtask
+
+endmodule

regression/verilog/typedef/typedef_name_collision1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+typedef_name_collision1.sv
+
+^EXIT=2$
+^SIGNAL=0$
+--
+--
+The name collision should be errored.

regression/verilog/typedef/typedef_name_collision1.sv

@@ -0,0 +1,8 @@
+module main;
+
+  typedef bit some_identifier;
+
+  // name collision
+  typedef bit some_identifier;
+
+endmodule

regression/verilog/typedef/typedef_name_collision2.desc

@@ -0,0 +1,7 @@
+CORE
+typedef_name_collision2.sv
+
+^file .* line 6: definition of symbol `some_identifier' conflicts with earlier definition at line 3$
+^EXIT=2$
+^SIGNAL=0$
+--

regression/verilog/typedef/typedef_name_collision2.sv

@@ -0,0 +1,8 @@
+module main;
+
+  wire some_identifier;
+
+  // name collision
+  typedef bit some_identifier;
+
+endmodule