Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Verilog: strengthen typing for generate constructs #352

Merged
merged 1 commit into from
Jan 23, 2024

Conversation

kroening
Copy link
Member

This uses types stronger than exprt for Verilog generate constructs.

@kroening kroening force-pushed the verilog-generate-typing branch from 699db59 to 2356c21 Compare January 22, 2024 21:34
This uses types stronger than exprt for Verilog generate constructs.
@kroening kroening force-pushed the verilog-generate-typing branch from 2356c21 to e930fa4 Compare January 22, 2024 21:40
@kroening kroening marked this pull request as ready for review January 22, 2024 21:42
@tautschnig tautschnig merged commit cfcf0f9 into main Jan 23, 2024
4 checks passed
@tautschnig tautschnig deleted the verilog-generate-typing branch January 23, 2024 11:11
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants