Merge pull request #350 from diffblue/elaborate_genvar

Verilog: genvar symbols now created during elaboration
diffblue · Jan 23, 2024 · a849576 · a849576
2 parents a9bc480 + 8947804
commit a849576
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Showing 3 changed files with 36 additions and 6 deletions.
diff --git a/src/verilog/Makefile b/src/verilog/Makefile
@@ -1,6 +1,6 @@
 SRC = expr2verilog.cpp \
       sva_expr.cpp \
-      verilog_elaborate_constants.cpp \
+      verilog_elaborate.cpp \
       verilog_expr.cpp \
       verilog_generate.cpp \
       verilog_interfaces.cpp \

diff --git a/src/verilog/verilog_elaborate_constants.cpp → src/verilog/verilog_elaborate.cpp b/src/verilog/verilog_elaborate_constants.cpp → src/verilog/verilog_elaborate.cpp
@@ -251,6 +251,30 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
       }
     }
   }
+  else if(decl_class == ID_verilog_genvar)
+  {
+    symbolt symbol{irep_idt{}, verilog_genvar_typet{}, mode};
+
+    symbol.module = module_identifier;
+    symbol.value.make_nil();
+
+    for(auto &declarator : decl.declarators())
+    {
+      DATA_INVARIANT(declarator.id() == ID_declarator, "must have declarator");
+
+      symbol.base_name = declarator.base_name();
+      symbol.location = declarator.source_location();
+
+      if(symbol.base_name.empty())
+        throw errort().with_location(decl.source_location())
+          << "empty symbol name";
+
+      symbol.name = hierarchical_identifier(symbol.base_name);
+      symbol.pretty_name = strip_verilog_prefix(symbol.name);
+
+      add_symbol(symbol);
+    }
+  }
 }
 
 void verilog_typecheckt::collect_symbols(const verilog_statementt &statement)
@@ -364,6 +388,15 @@ void verilog_typecheckt::collect_symbols(
     collect_symbols(to_verilog_initial(module_item).statement());
   }
   else if(module_item.id() == ID_generate_block)
+  {
+    auto &generate_block = to_verilog_generate_block(module_item);
+    for(auto &sub_module_item : generate_block.module_items())
+      collect_symbols(sub_module_item);
+  }
+  else if(module_item.id() == ID_generate_for)
+  {
+  }
+  else if(module_item.id() == ID_generate_if)
   {
   }
   else if(module_item.id() == ID_inst || module_item.id() == ID_inst_builtin)

diff --git a/src/verilog/verilog_interfaces.cpp b/src/verilog/verilog_interfaces.cpp
@@ -391,13 +391,10 @@ void verilog_typecheckt::interface_module_decl(
     interface_function_or_task(decl);
     return;
   }
-  else if(port_class == ID_verilog_genvar)
-  {
-    type = verilog_genvar_typet();
-  }
   else if(
     port_class == ID_input || port_class == ID_output ||
-    port_class == ID_output_register || port_class == ID_inout)
+    port_class == ID_output_register || port_class == ID_inout ||
+    port_class == ID_verilog_genvar)
   {
     // symbol already created during elaboration
     return;