Verilog: zero_extend now considers genvar

zero_extend now handles genvar-typed variables.
diffblue · Oct 31, 2024 · 6fa56eb · 6fa56eb
1 parent 6b0d346
commit 6fa56eb
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/regression/verilog/system-functions/low1.desc b/regression/verilog/system-functions/low1.desc
@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE broken-smt-backend
 low1.sv
 --module main --bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-This yields an error in the typechecker.
diff --git a/src/verilog/verilog_typecheck_expr.cpp b/src/verilog/verilog_typecheck_expr.cpp
@@ -2351,8 +2351,9 @@ Function: zero_extend
 
 static exprt zero_extend(const exprt &expr, const typet &type)
 {
-  auto old_width = expr.type().id() == ID_bool
-                     ? 1
+  auto old_width = expr.type().id() == ID_bool ? 1
+                   : expr.type().id() == ID_integer
+                     ? 32
                      : to_bitvector_type(expr.type()).get_width();
 
   // first make unsigned