Merge pull request #271 from diffblue/verilog-range

Verilog: rules for part select expressions
diffblue · Dec 11, 2023 · 27ece61 · 27ece61
2 parents e32bd10 + 498d6e3
commit 27ece61
Showing 1 changed file with 21 additions and 15 deletions.
diff --git a/src/verilog/parser.y b/src/verilog/parser.y
@@ -911,13 +911,6 @@ part_select:
 		{ init($$, ID_part_select); mto($$, $2); mto($$, $4); }
 	;
 
-indexed_part_select:
-	  '[' const_expression TOK_PLUSCOLON const_expression ']'
-		{ init($$, ID_indexed_part_select_plus); mto($$, $2); mto($$, $4); }
-        | '[' const_expression TOK_MINUSCOLON const_expression ']'
-		{ init($$, ID_indexed_part_select_minus); mto($$, $2); mto($$, $4); }
-	;
-
 // System Verilog standard 1800-2017
 // A.2.1.3 Type declarations
 
@@ -2616,15 +2609,30 @@ inc_or_dec_expression:
                 { init($$, ID_postdecrement); mto($$, $1); }
         ;
 
+constant_range:
+	  const_expression TOK_COLON const_expression
+		{ init($$, ID_part_select); mto($$, $1); mto($$, $3); }
+	;
+
+indexed_range:
+	  expression TOK_PLUSCOLON constant_expression
+		{ init($$, ID_indexed_part_select_plus); mto($$, $1); mto($$, $3); }
+	| expression TOK_MINUSCOLON constant_expression
+		{ init($$, ID_indexed_part_select_minus); mto($$, $1); mto($$, $3); }
+	;
+
+part_select_range:
+	  constant_range
+	| indexed_range
+	;
+
 // System Verilog standard 1800-2017
 // A.8.4 Primaries
 
 primary:  primary_literal
         | indexed_variable_lvalue
-	| indexed_variable_lvalue part_select
-		{ extractbits($$, $1, $2); }
-	| indexed_variable_lvalue indexed_part_select
-		{ extractbits($$, $1, $2); }
+	| indexed_variable_lvalue '[' part_select_range ']'
+		{ extractbits($$, $1, $3); }
 	| concatenation 
         | replication
         | function_subroutine_call
@@ -2651,10 +2659,8 @@ net_lvalue: variable_lvalue;
 
 variable_lvalue:
 	  indexed_variable_lvalue
-	| indexed_variable_lvalue part_select
-		{ extractbits($$, $1, $2); }
-	| indexed_variable_lvalue indexed_part_select
-		{ extractbits($$, $1, $2); }
+	| indexed_variable_lvalue '[' part_select_range ']'
+		{ extractbits($$, $1, $3); }
         | concatenation
           /* more generous than the rule below to avoid conflict */
         /*