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Verilog: reorder grammar to match 1800-2017 #442

Verilog: reorder grammar to match 1800-2017

Verilog: reorder grammar to match 1800-2017 #442

Triggered via pull request February 26, 2024 23:59
Status Success
Total duration 1m 49s
Artifacts

syntax-checks.yaml

on: pull_request
check-clang-format
1m 39s
check-clang-format
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