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Verilog: clean up base_name vs identifier in declarators #1182

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Verilog: clean up base_name vs identifier in declarators

Verilog: clean up base_name vs identifier in declarators #1182

Triggered via pull request February 4, 2024 20:48
@kroeningkroening
synchronize #364
verilog-fix-symbols
Status Success
Total duration 1m 24s
Artifacts –

pull-request-checks.yaml

on: pull_request
check-ubuntu-20_04-make-gcc
1m 2s
check-ubuntu-20_04-make-gcc
check-ubuntu-20_04-make-clang
1m 16s
check-ubuntu-20_04-make-clang
CentOS 8
54s
CentOS 8
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