Skip to content
Syntactic checks

Verilog: clean up base_name vs identifier in declarators #398

Sign in to view logs

Verilog: clean up base_name vs identifier in declarators

Verilog: clean up base_name vs identifier in declarators #398

Triggered via pull request February 2, 2024 19:52
@kroeningkroening
opened #364
verilog-fix-symbols
Status Success
Total duration 1m 5s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
56s
check-clang-format
Fit to window
Zoom out
Zoom in