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Syntactic checks

Verilog: elaborate wire symbols #392

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Verilog: elaborate wire symbols

Verilog: elaborate wire symbols #392

Triggered via pull request February 1, 2024 19:02
@kroeningkroening
synchronize #359
elaborate-wire
Status Success
Total duration 1m 8s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
53s
check-clang-format
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