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Verilog: move generate construct expansion into elaboration phase #1127

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Verilog: move generate construct expansion into elaboration phase

Verilog: move generate construct expansion into elaboration phase #1127

Triggered via pull request January 28, 2024 02:48
@kroeningkroening
synchronize #335
verilog-interleave-typechecking
Status Failure
Total duration 1m 38s
Artifacts –

pull-request-checks.yaml

on: pull_request
check-ubuntu-20_04-make-gcc
1m 20s
check-ubuntu-20_04-make-gcc
check-ubuntu-20_04-make-clang
1m 29s
check-ubuntu-20_04-make-clang
CentOS 8
1m 3s
CentOS 8
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3 errors
CentOS 8
Process completed with exit code 2.
check-ubuntu-20_04-make-gcc
Process completed with exit code 2.
check-ubuntu-20_04-make-clang
Process completed with exit code 2.