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Verilog: propagate constants of any type during synthesis #102

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Verilog: propagate constants of any type during synthesis

Verilog: propagate constants of any type during synthesis #102

Triggered via pull request December 8, 2023 15:10
@kroeningkroening
synchronize #248
synth-values-expr2
Status Success
Total duration 1m 23s
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syntax-checks.yaml

on: pull_request
check-clang-format
53s
check-clang-format
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