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Syntactic checks

SystemVerilog: delay expansion of string literals #1906

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SystemVerilog: delay expansion of string literals

SystemVerilog: delay expansion of string literals #1906

Triggered via pull request January 3, 2025 12:09
@kroeningkroening
synchronize #913
verilog-string-literals
Status Success
Total duration 1m 32s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
1m 22s
check-clang-format
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