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Merge pull request chipsalliance#1100 from hzeller/sort-indent-build
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Format BUILD files.
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hzeller authored Nov 11, 2021
2 parents d98e3b8 + d30a948 commit 60829f3
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Showing 4 changed files with 4 additions and 4 deletions.
2 changes: 1 addition & 1 deletion common/analysis/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -96,7 +96,7 @@ cc_library(
"//common/util:user_interaction",
"@com_google_absl//absl/status",
"@com_google_absl//absl/strings",
]
],
)

cc_test(
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2 changes: 1 addition & 1 deletion verilog/formatting/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -136,8 +136,8 @@ cc_library(
":token_annotator",
":tree_unwrapper",
"//common/formatting:format_token",
"//common/formatting:line_wrap_searcher",
"//common/formatting:layout_optimizer",
"//common/formatting:line_wrap_searcher",
"//common/formatting:token_partition_tree",
"//common/formatting:unwrapped_line",
"//common/formatting:verification",
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2 changes: 1 addition & 1 deletion verilog/tools/kythe/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -91,9 +91,9 @@ cc_library(
"//common/strings:compare",
"//common/util:logging",
"//verilog/analysis:verilog_project",
"@com_google_absl//absl/container:btree",
"@com_google_absl//absl/memory",
"@com_google_absl//absl/strings",
"@com_google_absl//absl/container:btree",
],
)

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2 changes: 1 addition & 1 deletion verilog/tools/lint/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -226,11 +226,11 @@ cc_binary(
srcs = ["verilog_lint.cc"],
visibility = ["//visibility:public"],
deps = [
"//common/analysis:violation_handler",
"//common/util:enum_flags",
"//common/util:file_util",
"//common/util:init_command_line",
"//common/util:logging",
"//common/analysis:violation_handler",
"//verilog/analysis:verilog_linter",
"//verilog/analysis:verilog_linter_configuration",
"@com_google_absl//absl/flags:flag",
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