16-bit MIPS Inspired Single-Cycle Processor

Created by: Tiffany Shum and Lani Wang

Inspired by Prof Marano and Harris & Harris's MIPS implementations.

Components Included

adder
alu
clock
controller
datapath
dff
dmem
imem
maindec
mux2
regfile
signext
sl1

CPU Diagram

We chose a single-cycle, non-pipelined implementation.

Instruction Set Architecture

Parameters

Operand & Instruction size: 16 bits
Byte Addressable
Immediate Size: 4 bits (-7 to 7)
Shamt Size: 4 bits
Opcode Size: 4 bits

Instruction Fields

The CPU supports 16 instructions from the core MIPS architecture set. For simplicity, the 16 instruction bits were divided evenly into four fields. The first is a 4-bit opcode, which combines the functionality of both ‘opcode’ and ‘funct’ from MIPS to determine which instruction should be performed. The following 3 fields represent input and output registers (R-type instructions), input/output register and the immediate (constant) to be used (I-type). For J-type instructions, the 12 bits are combined into one field that specifies an address.

Control Signals

Based on the 4-bit instruction opcode, 8 control signals are generated. ALUop, which determines which arithmetic operation is to be performed by the ALU, is generated by the ALU decoder. The rest are determined by the main decoder. They function as follows:

RegWrite – enables a write to one of the registers.
RegDst – determines whether the destination register is rd or rt
Branch – only used for beq, enables loading branch address to the PC.
MemWrite – enables a write to memory.
MemToReg – determines the source of a value written to a register.
Jump – enables loading a jump target address to the PC.
ALUsrc – determines whether the second source operand for ALU instructions is rt or the (sign-extended) immediate field.

Functionality of the Instruction Set

Registers Defined in Memory

Memory Usage

Memory consists of imem (instruction memory) and dmem (data memory). The instruction memory is stored in instructions.dat and is written in hex. When given the address specified by the PC, it returns the 16-bit instruction that is then sent to the control unit. The control decoders, based on the 4-bit opcode, decide all of the control signals needed for the other components. As for data memory, it is accessed when instructions like lw (load word) or sw (store word) are invoked.

Example Program: Fibonacci

Compiled to MIPS

addi $s2, $zero, 10
move $a0, $s2      
jal fib
beq $zero, $zero, END


fib: 

addi $sp, $sp, -12  
sw $ra, 0($sp)  
sw $s0, 4($sp) 
sw $a0, 8($sp)  

beq $a0, $zero, isZero
beq $a0, 1, isOne

#else if case
addi $a0, $a0, -1
jal fib
move $s0, $v0

lw $a0, 8($sp)
addi $a0, $a0, -2
jal fib
add $v0, $v0, $s0

lw $s0, 8($sp)
lw $ra, 0($sp)
addi $sp, $sp, 12
jr $ra


isZero:
lw $s0, 4($sp)
lw $ra, 0($sp)
addi $sp, $sp, 12
add $v0, $zero, $zero
jr $ra


isOne:
lw $s0, 4($sp)
lw $ra, 0($sp)
addiu $sp, $sp, 12
addi $v0, $zero, 1
jr $ra