Catalog of Verilog Components to Build and Simulate a MIPS-based RISC.

Anthony Noseryev, Nolan Griffith

This work is based off the MIPS Verilog code by Harris and Harris. We give credit to Professor Rob Marano [email protected] for guidance with this implementation.

See ISAArchitectureGreenSheet for ISA documentation.

The provided sample program is a recursive Fibonacci Sequence implementation. Attached is a small demonstration of the simulation process.

Instructions to Successfully Demo

To compile and simulate this CPU, use the following commands:

make clean compile simulate

For displaying the simulation with GTKWAVE, run:

make display

In GTKWAVE, select "tb_computer.vcd" as your SST. Highlight "dut or dut1" and select all signals of interest, then drag them to the Signal area on the right.

Once completed, navigate to Time -> Zoom -> Zoom Best Fit.

For cleanup:

make clean

Overall Design Explanation

Our CPU supports a modest collection of MIPS operations. Our ISA is modelled after RISC, specifically MIPS32, architecture, with 32 bits per word and 32 registers.

We implemented 8 simple ALU operations (listed in the ISAArchitectureGreenSheet), beq, j, jr, jal, lw and sw.

Our design is single-cycle as demonstrated by the timing diagrams below.

Our design features separate Data Memory and Instruction Memory, both of which have a capacity of 64 words by default.

Overall Design Diagrams

Our datapath emulates the following design, taken from Patterson and Hennessy, Computer Organization and Design, 6th ed.

Below is a diagram of our Data Memory and Instruction Memory the default capacity of 64 words.

Timing Diagrams

Attached below is a sample timing diagram for a program executing the following three simple instructions (R, I, and J-type respectively). Note that (ticks) is set to 10 ns and each instruction takes 10 ns to execute.

add $t2, $t0, $t1
addi $t2, $t0, 1
j 0