Feedback

catalog/adder/adder.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Andrew Yuan and Zachary Hsieh
 // 
 //     Create Date: 2023-02-07
 //     Module Name: adder
@@ -20,11 +20,17 @@ module adder
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-
+
+    input logic [n-1:0] a,
+    input logic [n-1:0] b,
+    output logic [n-1:0] y
 );
+
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
+    assign y = a + b;
+
 
 endmodule
 

catalog/adder/tb_adder.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_adder
@@ -14,25 +14,34 @@
 `define TB_ADDER
 
 `timescale 1ns/100ps
-`include "adder.sv"
+`include "./adder.sv"
 
 module tb_adder;
-    parameter n = 32;
-    logic [(n-1):0] a, b, y;
-
-   initial begin
-        $dumpfile("adder.vcd");
-        $dumpvars(0, uut);
-        $monitor("a = 0x%0h b = 0x%0h y = 0x%0h", a, b, y);
-    end
-
-    initial begin
-        a <= #n'hFFFFFFFF;
-        b <= #n'hFFFFFFFF;
-    end
-
-    adder uut(
-        .A(a), .B(b), .Y(y)
-    );
+   parameter N = 32;
+
+   reg [N-1:0] A;
+   reg [N-1:0] B;   //inputs are reg for test bench
+
+   wire [N-1:0] Y;     //outputs are wire for test bench
+
+   //
+   // ---------------- INITIALIZE TEST BENCH ----------------
+   //
+
+   //apply input vectors
+   initial begin: apply_stimulus
+   A = 32'b00110101100100111001111111000000;
+   B = 32'b10101111010000000101010001011001;
+   $display("A=%b B=%b Y=%b\n", A, B, Y);
+      $finish;
+   end
+
+
+   //
+   // ---------------- INSTANTIATE UNIT UNDER TEST (UUT) ----------------
+   //
+   adder uut(.a(A), .b(B), .y(Y));
+
 endmodule
+
 `endif // TB_ADDER

catalog/alu/alu.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: alu
@@ -20,11 +20,36 @@ module alu
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
+
+    input logic clk,
+    input logic [n-1:0] a, 
+    input logic [n-1:0] b,
+    input logic [2:0] op,
+    output logic [n-1: 0] y,
+    output logic zero
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
 
+
+    assign zero = (y==0);
+
+    always @(a,b,op) begin
+        case(op)
+            3'b000: y = a & b;  //and
+            3'b001: y = a | b;  //or
+            3'b010: y = a + b;  //add
+            3'b011: y = ~(a | b);   //nor
+            3'b100: y = a-b;    //subtract
+            3'b101: y = (a < b) ? {n{1'b1}} : {n{1'b0}};   //set less than
+            3'b110: y = a << b[4:0]; //sll; we have 32 bits, so our max shift amount of 32, which is 5 bits of b if we assume that b is the shift amount and a is the shifted number
+            3'b111: y = a >> b[4:0]; //slr
+        endcase
+    end
+
+
+
 endmodule
 
 `endif // ALU

catalog/alu/tb_alu.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh and Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_alu
@@ -17,7 +17,69 @@
 `include "alu.sv"
 
 module tb_alu;
-    parameter n = 32;
+    parameter N = 32;
+
+    reg [N-1:0] A;
+    reg [N-1:0] B;
+    reg [2:0] OP;
+    reg CLK;
+
+    wire [N-1:0] Y;
+
+    initial begin : initialize_variable
+    A = 0;
+    B = 0;
+    end
+
+    always begin : clock
+        #5 CLK = ~CLK;
+    end
+
+    always @(posedge CLK) 
+    begin
+        case (OP)
+            3'b000: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b001: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b010: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b011: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b100: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b101: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b110: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+            3'b111: $display("A=%b B=%b OP=%b Y=%b Zero=%b\n", A, B, OP, Y, ZERO);
+        endcase
+    end
+
+
+    //apply input vectors
+    initial begin
+    $dumpfile("tb_alu.vcd");
+    $dumpvars(0, tb_alu.uut);
+    A = 32'b11100000010100010110011110101010;
+    B = 32'b01100001100101100100101001011111;
+    CLK = 0;
+    #10;
+    OP = 3'b000;
+    #10;
+    OP = 3'b001;
+    #10;
+    OP = 3'b010;
+    #10;
+    OP = 3'b011;
+    #10;
+    OP = 3'b100;
+    #10;
+    OP = 3'b101;
+    #10;
+    OP = 3'b110;
+    #10;
+    $finish;
+end
+
+//
+// ---------------- INSTANTIATE UNIT UNDER TEST (UUT) ----------------
+//
+alu uut(.a(A), .b(B), .clk(CLK), .op(OP), .zero(ZERO), .y(Y));
+
 
 endmodule
 `endif // TB_ALU

catalog/aludec/aludec.sv

@@ -1,11 +1,11 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: aludec
-//     Description: 32-bit RISC ALU decoder
+//     Description: 16-bit RISC ALU decoder
 //
 // Revision: 1.0
 //
@@ -16,15 +16,36 @@
 `timescale 1ns/100ps
 
 module aludec
-    #(parameter n = 32)(
+    #(parameter n = 16)(
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-
+    input logic [5:0] funct,      //
+    input logic [1:0] aluop,      //Operation type
+    output logic [2:0] alucontrol //ALU operations
+    );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-
+    always @*
+    begin
+        case(aluop)                  //I-type instructions
+        2'b11: alucontrol <= 3'b010; // addi (for lw/sw/jr/addi)
+        2'b10: alucontrol <= 3'b100; // subi (for beq)
+        2'b01: alucontrol <= 3'b101; //slt (for slti)
+            default: case(funct)           // R-type instructions
+                6'b100100: alucontrol <= 3'b000; // and
+                6'b100101: alucontrol <= 3'b001; // or
+                6'b100000: alucontrol <= 3'b010; // add
+                6'b100111: alucontrol <= 3'b011; // nor
+                6'b100010: alucontrol <= 3'b100; // subtract
+                6'b101010: alucontrol <= 3'b101; // slt
+                6'b000000: alucontrol <= 3'b110; // sll
+                6'b000010: alucontrol <= 3'b111; // slr
+                default: alucontrol <= 3'bxxx; // ???
+            endcase
+        endcase
+    end
 endmodule
 
 `endif // ALUDEC

catalog/aludec/tb_aludec.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Zachary Hsieh & Andrew Yuan
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_aludec
@@ -17,7 +17,54 @@
 `include "aludec.sv"
 
 module tb_aludec;
-    parameter n = 32;
+ // Inputs
+    reg [5:0] funct;
+    reg [1:0] aluop;
+
+    // Outputs
+    wire [2:0] alucontrol;
+
+    // Instantiate the Unit Under Test (UUT)
+    aludec uut (
+        .funct(funct),
+        .aluop(aluop),
+        .alucontrol(alucontrol)
+    );
+
+    // Testbench logic
+    initial begin
+        // Initialize Inputs
+        funct = 0;
+        aluop = 0;
+
+        // Wait for global reset
+        #100;
+
+        // Test various combinations
+        funct = 6'b100000; aluop = 2'b00; #100;
+        funct = 6'b100101; aluop = 2'b00; #100;
+        funct = 6'b100000; aluop = 2'b00; #100;
+        funct = 6'b100111; aluop = 2'b00; #100;
+        funct = 6'b100010; aluop = 2'b00; #100;
+        funct = 6'b101010; aluop = 2'b00; #100;
+        funct = 6'b000000; aluop = 2'b00; #100;
+        funct = 6'b000010; aluop = 2'b00; #100;
+
+        funct = 6'bxxxxxx; aluop = 2'b01; #100; // Tests for partial don't care in `funct`
+        funct = 6'bxxxxxx; aluop = 2'b10; #100; // Tests for partial don't care in `funct`
+        funct = 6'bxxxxxx; aluop = 2'b11; #100; // Tests for partial don't care in `funct`
+
+        // Additional test for undefined operation
+        funct = 6'b010101; aluop = 2'b11; #100;
+
+        // Finish simulation
+        $finish;
+    end
+
+    // Monitor changes
+    initial begin
+        $monitor("At time %t, funct = %b, aluop = %b, alucontrol = %b", $time, funct, aluop, alucontrol);
+    end
 
 endmodule
 `endif // TB_ALUDEC

catalog/computer/mult-prog_exe

@@ -1,11 +1,11 @@
-2002000a
-2003000f
-00620018
-00001010
-00001012
-ac020054
-00000000
-00000000
+0c040004
+0c050004
+0C060002
+0C070005
+00854020
+00c74820
+01098022
+02001020
 00000000
 00000000
 00000000