Special Thanks to Professor Marano for his guidance and support throughout the semester.
In this project, we implemented a 16-bit RISC Single Cycle CPU. This CPU has Von Neumann architecture and is implemented with verilog. The following components are utilized in the making of the CPU: adder,alu, aludec, clock, computer, controller, cpu, datapath, dff, dmem, imem, maindec, mux2, regfile, signext, and sl2.
Our CPU has 16 instructions from the MIPS architecture set. The first 4 bits are the opcode. The following 3 groups of 4 bits are the input/output registers, used for R, I, and J type instructions.
16-bit MIPS-based Single Cycle CPU
Tthe control signals control how information travels within the CPU depending on the opcode supplied to the controller.
memory is split into dmem and imem
imem: Returns 16-bit instruction that is sent off to control unit when given the address specified by the PC
dmem: This is where memory is written. Utilized by sw and lw
To test the functionality of our CPU, we would run the fibonacci sequence based on the above except with the machine code on the right replaced with appropriate machine code as defined by our ISA.
Although our total project was unable to compile, we learned a lot from designing and debugging the invidivual modules (which should all work as tested in EDAplayground). Future design considerations include a programmatic assembler, cache support, and pipelining.