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README.md

@@ -1,3 +1,18 @@
+# 32 bit MIPS-wannabe Processor
+Isaac Moore and Morris Madeb
+
+
+
+![Opcodes and functions](https://github.com/cooper-union-ece-251-marano/final-project-ece-251-spring-2024-comparchcrunch/assets/44485789/4013d522-ea90-46d7-9a6f-358f8ff4446e)
+Defined functions
+
+![instruction format](https://github.com/cooper-union-ece-251-marano/final-project-ece-251-spring-2024-comparchcrunch/assets/44485789/6d91fd3a-0b64-4fc6-941d-29505cac87e8)
+R, I, and J Formating
+
+![e90449dc-7ca4-4dd5-940c-21ea568a4e40](https://github.com/cooper-union-ece-251-marano/final-project-ece-251-spring-2024-comparchcrunch/assets/44485789/c41e345e-fa31-405a-bd34-1f0094a705eb)
+Datapath
+
+[![Review Assignment Due Date](https://classroom.github.com/assets/deadline-readme-button-24ddc0f5d75046c5622901739e7c5dd533143b0c8e959d652212380cedb1ea36.svg)](https://classroom.github.com/a/pelSJLGu)
 # Catalog of Verilog Components to Build and Simulate a MIPS-based RISC.
 
 This work is based off the MIPS Verilog code by [Harris and Harris](https://pages.hmc.edu/harris/ddca/ddca2e.html)

catalog/adder/adder.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: adder
@@ -17,14 +17,16 @@
 
 module adder
     #(parameter n = 32)(
-    //
-    // ---------------- PORT DEFINITIONS ----------------
-    //
-
-);
-    //
-    // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
-    //
+        //
+        // ---------------- PORT DEFINITIONS ----------------
+        //
+        input [(n-1):0] a, b;
+        output reg [(n-1):0] c;
+    );
+   //
+   // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
+   //
+   assign c = a + b;
 
 endmodule
 

catalog/adder/clean.ps1

@@ -0,0 +1,23 @@
+<#
+ # File: 	clean.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+# $COMPONENT is named in config.ps1
+# Do not forget to add that file in the same directory as this file and set the variable
+$ScriptDirectory = Split-Path -Path $MyInvocation.MyCommand.Definition -Parent
+try {
+    . ("$ScriptDirectory\config.ps1")
+}
+catch {
+    Write-Host "Error while loading supporting PowerShell Scripts"
+    [Environment]::Exit(1)
+}
+
+# Clean up from last run
+Write-Output "Removing files: $filesToRemove"
+$filesToRemove | ForEach-Object { Remove-Item -Path $_ -Force -ErrorAction SilentlyContinue -Confirm:$false}
+
+Write-Output "Finished cleaning up files."

catalog/adder/config.ps1

@@ -0,0 +1,23 @@
+<#
+ # File: 	config.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+ $COMPONENT = "adder"
+ #
+ $SRC = "$COMPONENT.sv"
+ $TESTBENCH = "tb_$COMPONENT.sv"
+ $TBOUTPUT = "tb_$COMPONENT.vcd"
+ $filesToRemove = @("$COMPONENT", "$TBOUTPUT")
+
+ # TOOLS
+ # You need to update the paths below to the tools in your system
+ $COMPILER = "C:\ProgramData\chocolatey\bin\iverilog.exe"
+ $SIMULATOR = "C:\ProgramData\chocolatey\bin\vvp.exe"
+ $VIEWER = "C:\ProgramData\chocolatey\bin\gtkwave.exe" # GUI app
+ # TOOL OPTIONS
+ $COFLAGS = "-g2012"
+ $SFLAGS = "-M ."		#SIMULATOR FLAGS
+ $SOUTPUT = "-lxt2"		#SIMULATOR OUTPUT TYPE

catalog/adder/display.ps1

@@ -0,0 +1,27 @@
+<#
+ # File: 	display.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+# $COMPONENT is named in config.ps1
+# Do not forget to add that file in the same directory as this file and set the variable
+$ScriptDirectory = Split-Path -Path $MyInvocation.MyCommand.Definition -Parent
+try {
+    . ("$ScriptDirectory\config.ps1")
+}
+catch {
+    Write-Host "Error while loading supporting PowerShell Scripts"
+    [Environment]::Exit(1)
+}
+
+#
+# Display Verilog module with testbench
+# $(SIMULATOR) $(SFLAGS) $(COMPONENT) $(TESTBENCH) $(SOUTPUT)
+$displayProcessOptions = @{
+    FilePath = "$VIEWER"
+    ArgumentList = @("$TBOUTPUT")
+    UseNewEnvironment = $true
+}
+Start-Process @displayProcessOptions -NoNewWindow -Wait

catalog/adder/makefile.ps1

@@ -0,0 +1,44 @@
+<#
+ # File: 	makefile.ps1
+ # Author: 	Prof. Rob Marano
+ # Build and test file for Verilog on Windows using PowerShell
+ # Note: icarus verilog and gtkwave must be installed
+ #>
+
+# $COMPONENT is named in config.ps1
+# Do not forget to add that file in the same directory as this file and set the variable
+$ScriptDirectory = Split-Path -Path $MyInvocation.MyCommand.Definition -Parent
+try {
+    . ("$ScriptDirectory\config.ps1")
+}
+catch {
+    Write-Host "Error while loading supporting PowerShell Scripts"
+    [Environment]::Exit(1)
+}
+
+# Clean up from last run
+Write-Output "Removing files: $filesToRemove"
+#Remove-Item -Path $filesToRemove -ErrorAction SilentlyContinue -Confirm
+$filesToRemove | ForEach-Object { Remove-Item -Path $_ -Force -ErrorAction SilentlyContinue -Confirm:$false}
+
+#
+# Compile Verilog file
+#
+# $COMPILER $COFLAGS -o $COMPONENT $TESTBENCH $SRC
+$compileProcessOptions = @{
+    FilePath = "$COMPILER"
+    ArgumentList = @("$COFLAGS", "-o", "$COMPONENT", "$TESTBENCH", "$SRC")
+    UseNewEnvironment = $true
+}
+Start-Process -NoNewWindow -Wait @compileProcessOptions
+
+#
+# Simulate Verilog module with testbench
+# $(SIMULATOR) $(SFLAGS) $(COMPONENT) $(TESTBENCH) $(SOUTPUT)
+$simulateProcessOptions = @{
+    FilePath = "$SIMULATOR"
+    ArgumentList = @("$SFLAGS", "$COMPONENT", "$SOUTPUT")
+    UseNewEnvironment = $true
+}
+Write-Output @simulateProcessOptions
+Start-Process @simulateProcessOptions -NoNewWindow -Wait

catalog/adder/tb_adder.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: tb_adder
@@ -18,21 +18,28 @@
 
 module tb_adder;
     parameter n = 32;
-    logic [(n-1):0] a, b, y;
+    logic [(n-1):0] a, b, out;
 
    initial begin
-        $dumpfile("adder.vcd");
+        $dumpfile("tb_adder.vcd");
         $dumpvars(0, uut);
-        $monitor("a = 0x%0h b = 0x%0h y = 0x%0h", a, b, y);
+        $monitor("a = 0x%0h b = 0x%0h out = 0x%0h", a, b, out);
     end
 
     initial begin
-        a <= #n'hFFFFFFFF;
-        b <= #n'hFFFFFFFF;
+        a <= #n'h01B30FFF;
+        b <= #n'hFFA5FFFF;
+        #10
+        a <= #n'987654321;
+        b <= #n'123456789;
+        #10
+        a <= #n'h01000001;
+        b <= #n'101010101;
+        $finish;
     end
 
     adder uut(
-        .A(a), .B(b), .Y(y)
+        .a(a), .b(b), .c(out)
     );
 endmodule
 `endif // TB_ADDER

catalog/alu/alu.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: YOUR NAMES
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: alu
@@ -20,10 +20,41 @@ module alu
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
+    input logic clk,
+    input logic [2:0] alucontrol,
+    input logic [(n-1):0] a, b,
+    output logic [(n-1):0] out,
+    output logic zero
 );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
+    logic [(2*n-1):0] HILO;
+
+    assign zero = (result == {n{1'b0}});
+
+    initial begin 
+        HILO = {(2*n){1'b0}};
+    end
+
+    always@(alucontrol,a,b) begin
+        case(alucontrol)
+            3'b000: result = a & b; //and
+            3'b001: result = a | b; //or
+            3'b010: result = ~(a | b); //nor
+            3'b011: result = a + b; //add
+            3'b100: result = a - b; //sub
+            3'b101: result = HILO[(2*n-1):n]; //mfhi
+            3'b110: result = HILO[(n-1):0]; //mflo
+            3'b111: result = (a<b)?1:0; //slt
+        endcase
+    end
+
+    always@(negedge clk) begin
+        case(alucontrol)
+            3'b101: HILO = a * b;
+        endcase
+    end
 
 endmodule
 

catalog/aludec/aludec.sv

@@ -16,15 +16,35 @@
 `timescale 1ns/100ps
 
 module aludec
-    #(parameter n = 32)(
+    #(parameter n = 32, r = 6)(
     //
     // ---------------- PORT DEFINITIONS ----------------
     //
-
+    input logic [(r-1):0] = funct,
+    input [1:0] aluop,
+    output reg [2:0] alucontrol
+    );
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
-
+    always@(*) begin
+        case(aluop)
+            2'b00: alucontrol <= 3'b010; //addi
+            2'b01: alucontrol <= 3'b110; //subi
+            default: case(funct)
+                6'b100000: alucontrol <= 3'b011; //add
+                6'b100010: alucontrol <= 3'b100; //sub
+                6'b100100: alucontrol <= 3'b000; //and
+                6'b100101: alucontrol <= 3'b001; //or
+                6'b100111: alucontrol <= 3'b010; //nor
+                6'b011000: alucontrol <= 3'b101; //mult
+                6'b010000: alucontrol <= 3'b101; //move hi
+                6'b010000: alucontrol <= 3'b110; //move lo
+                6'b101010: alucontrol <= 3'b111; //slt
+                default:   alucontrol <= 3'bxxx; //Illegal function
+            endcase
+        endcase
+    end
 endmodule
 
 `endif // ALUDEC

catalog/clock/clock.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: clock
@@ -55,4 +55,4 @@ module clock
     end
 endmodule
 
-`endif // CLOCK
+`endif // CLOCK

catalog/clock/tb_clock.sv

@@ -21,7 +21,7 @@ module tb_clock;
     logic enable;
 
    initial begin
-        $dumpfile("clock.vcd");
+        $dumpfile("tb_clock.vcd");
         $dumpvars(0, uut);
         //$monitor("enable = %b clk = %b", enable, clk);
         $monitor("time=%0t \t enable=%b clk=%b",$realtime, enable, clk);

catalog/computer/computer.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: computer
@@ -31,6 +31,7 @@ module computer
     //
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
+    //maybe wire not logic
     logic [(n-1):0] pc, instr, readdata;
 
     // computer internal components
@@ -44,4 +45,4 @@ module computer
 
 endmodule
 
-`endif // COMPUTER
+`endif // COMPUTER

catalog/controller/controller.sv

@@ -1,7 +1,7 @@
 //////////////////////////////////////////////////////////////////////////////////
 // The Cooper Union
 // ECE 251 Spring 2024
-// Engineer: Prof Rob Marano
+// Engineer: Isaac Moore, Morris Madeb
 // 
 //     Create Date: 2023-02-07
 //     Module Name: controller
@@ -35,15 +35,14 @@ module controller
     // ---------------- MODULE DESIGN IMPLEMENTATION ----------------
     //
     logic [1:0] aluop;
-    logic       branch;
+    logic branch;
 
     // CPU main decoder
     maindec md(op, memtoreg, memwrite, branch, alusrc, regdst, regwrite, jump, aluop);
     // CPU's ALU decoder
     aludec  ad(funct, aluop, alucontrol);
 
   assign pcsrc = branch & zero;
-
 endmodule
 
 `endif // CONTROLLER