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Ilona #2

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cefeb5c
ALU file
ilona403 May 13, 2023
758e320
i dunno
ilona403 May 14, 2023
5766034
yeah
ilona403 May 14, 2023
45a81fe
Added cpu
ilona403 May 14, 2023
2042e3b
Changed variables
ilona403 May 14, 2023
48fe054
hehe
ilona403 May 14, 2023
c07346d
fixed alu
ilona403 May 14, 2023
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97 changes: 97 additions & 0 deletions Alu/alu.sv
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//////////////////////////////////////////////////////////////////////////////////
// The Cooper Union //
// ECE 251 Spring 2023 //
// Engineers: Ridwan Hussain and Ilona Lameka //
// //
// Create Date: 2023-05-13 //
// Module Name: alu //
// Description: ALU //
// //
// Revision: 1.0 //
// //
//////////////////////////////////////////////////////////////////////////////////

`ifndef ALU
`define ALU

`timescale 1ns/100ps

module alu(clk, a, b, alucontrol, result, pc, zero);

input logic clk;
input logic [31:0] a, b;
input logic [2:0] alucontrol;
output logic [31:0] result, pc;
output logic zero;


//
// ---------------- MODULE DESIGN IMPLEMENTATION ----------------
//
logic [31:0] condinvb, sum;
logic [63:0] HiLo;

assign zero = (result == {32{1'b0}}); // zero result control signal

// initialize the internal HiLo register used in multiplying two 32-bit numbers = a 64-bit number.
initial
begin
HiLo = 64'b0;
end

always @(a,b,alucontrol) begin
case (alucontrol)
4'b0000: result = a + b; // add
4'b0001: result = a + (~b + 1'b1); // sub
4'b0100: result = a << b; //sl
4'b0101: result = a >> b; //sr
4'b0110: result = a & b; // and
4'b0111: result = a | b; // or
4'b1000: result = a^b; // xor
4'b1001: result = ~(a | b); //nor
4'b1010: result = a; //jr
4'b1011: result = ~(a & b); // nand
4'b1100: result = ~(a); //not

4'b1101: begin // slt
if (a[31] != b[31])
if (a[31] > b[31])
result = 1;
else
result = 0;
else
if (a < b)
result = 1;
else
result = 0;
end
4'1110: begin
if (a[31] != b[31])
if (a[31] < b[31])
result = 1;
else
result = 0;
else
if (a > b)
result = 1;
else
result = 0;
end
endcase
end

//Multiply and divide results are only stored at clock falling edge.
always @(negedge clk) begin
case (alucontrol)
4'b0010: HiLo = a * b; // mult
4'b0011: // div
begin
HiLo[31:0] = a / b;
HiLo[63:32] = a % b;
end
endcase
end

endmodule //alu

`endif
31 changes: 16 additions & 15 deletions AluDec/aluDec.sv
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Expand Up @@ -31,24 +31,25 @@ module aluDec(op, aluop, alucontrol);
2'b11: alucontrol <= 4'b0001; // sub
default:
case(op)
5'b01000: alucontrol <= 4'b0000; // add
5'b01001: alucontrol <= 4'b0001; // sub
5'b01010: alucontrol <= 4'b0010; // mult
5'b01011: alucontrol <= 4'b0011; // div
5'b01100: alucontrol <= 4'b0100; // sl
5'b01101: alucontrol <= 4'b0101; // sr
5'b01110: alucontrol <= 4'b0110; // and
5'b01111: alucontrol <= 4'b0111; // or
5'b10000: alucontrol <= 4'b1000; // xor
5'b10001: alucontrol <= 4'b1001; // nor
5'b10010: alucontrol <= 4'b1010; // jr
5'b10011: alucontrol <= 4'b1011; // nand
5'b10100: alucontrol <= 4'b1100; // not
5'b10101: alucontrol <= 4'b1101; // slt
5'b10110: alucontrol <= 4'b1110; // sgt
5'b00001: alucontrol <= 4'b0000; // add
5'b01001: alucontrol <= 4'b0001; // sub
5'b01010: alucontrol <= 4'b0010; // mult
5'b01011: alucontrol <= 4'b0011; // div
5'b01100: alucontrol <= 4'b0100; // sl
5'b01101: alucontrol <= 4'b0101; // sr
5'b01110: alucontrol <= 4'b0110; // and
5'b01111: alucontrol <= 4'b0111; // or
5'b10000: alucontrol <= 4'b1000; // xor
5'b10001: alucontrol <= 4'b1001; // nor
5'b10010: alucontrol <= 4'b1010; // jr
5'b10011: alucontrol <= 4'b1011; // nand
5'b10100: alucontrol <= 4'b1100; // not
5'b10101: alucontrol <= 4'b1101; // slt
5'b10110: alucontrol <= 4'b1110; // sgt
default: alucontrol <= 4'bxxxx; // ???
endcase
endcase

end

endmodule //aluDec
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41 changes: 41 additions & 0 deletions Computer/computer.sv
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//////////////////////////////////////////////////i///////////////////////////////
// The Cooper Union //
// ECE 251 Spring 2023 //
// Engineers: Ridwan Hussain and Ilona Lameka //
// //
// Create Date: 2023-05-14 //
// Module Name: computer //
// Description: Computer //
// //
// Revision: 1.0 //
// //
//////////////////////////////////////////////////////////////////////////////////

`ifndef COMPUTER
`define COMPUTER

`timescale 1ns/100ps

`include "../Cpu/cpu.sv"
`include "../Imem/imem.sv"
`include "../Dmem/dmem.sv"

module computer(clk, reset, writedate, dataadr, memwrite);
input logic clk reset;
input logic [31:0] writedata, dataadr;
output logic memwrite;

logic [31:0] pc, instr, readdata;

// computer internal components

// the RISC CPU
cpu mips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata);
// the instruction memory ("text segment") in main memory
imem imem(pc[7:2], instr);
// the data memory ("data segment") in main memory
dmem dmem(clk, memwrite, dataadr, writedata, readdata);

endmodule

`endif // COMPUTER
4 changes: 2 additions & 2 deletions ControlUnit/controller.sv
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Expand Up @@ -19,10 +19,10 @@
`include "../MainDec/mainDec.sv"
`include "../AluDec/aluDec.sv"

module controller(op, zero, regdst, jump, memread, memtoreg, aluop, memwrite, alusrc, regwrite, pcsrc);
module controller(op, zero, regdst, jump, memtoreg, aluop, memwrite, alusrc, regwrite, pcsrc, alucontrol);
input logic [4:0]op;
input logic zero;
output logic regdst, branch, jump, memread, memtoreg, aluop, memwrite, alusrc, regwrite, pcsrc;
output logic regdst, branch, jump, memtoreg, memwrite, alusrc, regwrite, pcsrc;
output logic [3:0] alucontrol;

logic [1:0] aluop;
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41 changes: 41 additions & 0 deletions Cpu/cpu.sv
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//////////////////////////////////////////////////////////////////////////////////
// The Cooper Union //
// ECE 251 Spring 2023 //
// Engineers: Ridwan Hussain and Ilona Lameka //
// //
// Create Date: 2023-05-14 //
// Module Name: cpu //
// Description: CPU //
// //
// Revision: 1.0 //
// //
//////////////////////////////////////////////////////////////////////////////////
`ifndef CPU
`define CPU

`timescale 1ns/100ps

`include "../ControlUnit/controller.sv"
`include "../Datapath/datapath.sv"

module cpu(clk, reset, pc, instr, memwrite,aluout, writedate, readdate);


input logic clk, reset;
output logic [31:0] pc;
input logic [31:0] instr;
output logic memwrite;
output logic [31:0] aluout, writedata,
input logic [31:0] readdata

logic memtoreg, alusrc, regdst, regwrite, jump, pcsrc, zero;
logic [3:0] alucontrol;

controller c(instr[(31):27], zero, regdst, jump, memtoreg, aluop, memwrite, alusrc, regwrite, pcsrc, alucontrol);


datapath dp(clk, reset, .dffEnable(1) memtoreg, pcsrc,alusrc, regdst, regwrite, jump, alucontrol, instr, readdate, zero, pc, aluout, writedata);

endmodule

`endif // CPU