Add sh1107

cnlohr · Jun 22, 2024 · 84d13f2 · 84d13f2
1 parent 4a959f4
commit 84d13f2
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Showing 2 changed files with 68 additions and 3 deletions.
diff --git a/examples/i2c_oled/ssd1306.h b/examples/i2c_oled/ssd1306.h
@@ -14,7 +14,7 @@
 #define SSD1306_PSZ 32
 
 // characteristics of each type
-#if !defined (SSD1306_64X32) && !defined (SSD1306_128X32) && !defined (SSD1306_128X64)
+#if !defined (SSD1306_64X32) && !defined (SSD1306_128X32) && !defined (SSD1306_128X64) && !defined (SH1107_128x128)
 	#error "Please define the SSD1306_WXH resolution used in your application"
 #endif
 
@@ -38,6 +38,15 @@
 #define SSD1306_OFFSET 0
 #endif
 
+#ifdef SH1107_128x128
+#define SH1107
+#define SSD1306_FULLUSE
+#define SSD1306_W 128
+#define SSD1306_H 128
+#define SSD1306_FULLUSE
+#define SSD1306_OFFSET 0
+#endif
+
 /*
  * send OLED command byte
  */
@@ -92,6 +101,29 @@ uint8_t ssd1306_data(uint8_t *data, uint8_t sz)
 // OLED initialization commands for 128x32
 const uint8_t ssd1306_init_array[] =
 {
+#ifdef SH1107
+	SSD1306_DISPLAYOFF,               // Turn OLED off
+	0x00,                             // Low column
+	0x10,                             // High column
+	0xb0,                             // Page address
+	0xdc, 0x00,                       // Set Display Start Line  (Where in memory it reads from)
+	SSD1306_SETCONTRAST, 0x6f,        // Set constrast
+	SSD1306_COLUMNADDR,               // Set memory addressing mode
+	SSD1306_DISPLAYALLON_RESUME,      // normal (as opposed to invert colors, always on or off.)
+	SSD1306_SETMULTIPLEX, (SSD1306_H-1), // Iterate over all 128 rows (Multiplex Ratio)
+	SSD1306_SETDISPLAYOFFSET, 0x00,   // Set display offset // Where this appears on-screen  (Some displays will be different)
+	SSD1306_SETDISPLAYCLOCKDIV, 0xf0, // Set precharge properties.  THIS IS A LIE  This has todo with timing.  <<< This makes it go brrrrrrrrr
+	SSD1306_SETPRECHARGE, 0x1d,       // Set pre-charge period  (This controls brightness)
+	SSD1306_SETVCOMDETECT, 0x35,      // Set vcomh
+	SSD1306_SETSTARTLINE | 0x0,            // 0x40 | line
+	0xad, 0x80,                       // Set Charge pump
+	SSD1306_SEGREMAP, 0x01,           // Default mapping
+	SSD1306_SETPRECHARGE, 0x06,       // ???? No idea what this does, but this looks best.
+	SSD1306_SETCONTRAST, 0xfe,        // Set constrast
+	SSD1306_SETVCOMDETECT, 0xfe,      // Set vcomh
+	SSD1306_SETMULTIPLEX, (SSD1306_H-1), // 128-wide.
+	SSD1306_DISPLAYON, // Display on.
+#else
     SSD1306_DISPLAYOFF,                    // 0xAE
     SSD1306_SETDISPLAYCLOCKDIV,            // 0xD5
     0x80,                                  // the suggested ratio 0x80
@@ -121,6 +153,7 @@ const uint8_t ssd1306_init_array[] =
     SSD1306_DISPLAYALLON_RESUME,           // 0xA4
     SSD1306_NORMALDISPLAY,                 // 0xA6
 	SSD1306_DISPLAYON,	                   // 0xAF --turn on oled panel
+#endif
 	SSD1306_TERMINATE_CMDS                 // 0xFF --fake command to mark end
 };
 
@@ -155,6 +188,25 @@ void ssd1306_refresh(void)
 {
 	uint16_t i;
 
+#ifdef SH1107
+
+#define SSD1306_W 128
+#define SSD1306_H 128
+	int x, y;
+
+	ssd1306_cmd(SSD1306_MEMORYMODE); // vertical addressing mode.
+
+	for(y=0;y<SSD1306_H/8;y++)
+	{
+		ssd1306_cmd(0xb0 | y);
+		ssd1306_cmd( 0x00 | (0&0xf) ); 
+		ssd1306_cmd( 0x10 | (0>>4) );
+		ssd1306_data(&ssd1306_buffer[y*4*SSD1306_PSZ+0*SSD1306_PSZ], SSD1306_PSZ);
+		ssd1306_data(&ssd1306_buffer[y*4*SSD1306_PSZ+1*SSD1306_PSZ], SSD1306_PSZ);
+		ssd1306_data(&ssd1306_buffer[y*4*SSD1306_PSZ+2*SSD1306_PSZ], SSD1306_PSZ);
+		ssd1306_data(&ssd1306_buffer[y*4*SSD1306_PSZ+3*SSD1306_PSZ], SSD1306_PSZ);
+	}
+#else
 	ssd1306_cmd(SSD1306_COLUMNADDR);
 	ssd1306_cmd(SSD1306_OFFSET);   // Column start address (0 = reset)
 	ssd1306_cmd(SSD1306_OFFSET+SSD1306_W-1); // Column end address (127 = reset)
@@ -196,6 +248,8 @@ void ssd1306_refresh(void)
 		}
 	}
 #endif
+#endif
+
 }
 
 /*

diff --git a/examples/i2c_oled/ssd1306_i2c.h b/examples/i2c_oled/ssd1306_i2c.h
@@ -321,17 +321,28 @@ uint8_t ssd1306_pkt_send(uint8_t *data, uint8_t sz, uint8_t cmd)
 uint8_t ssd1306_i2c_init(void)
 {
 	// Enable GPIOC and I2C
-	RCC->APB2PCENR |= RCC_APB2Periph_GPIOC;
 	RCC->APB1PCENR |= RCC_APB1Periph_I2C1;
+
+#ifdef CH32V20x
+	RCC->APB2PCENR |= RCC_APB2Periph_GPIOB;
+	// PB7 is SDA, 10MHz Output, alt func, open-drain
+	GPIOB->CFGLR &= ~(0xf<<(4*7));
+	GPIOB->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*7);
 
+	// PB6 is SCL, 10MHz Output, alt func, open-drain
+	GPIOB->CFGLR &= ~(0xf<<(4*6));
+	GPIOB->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*6);
+#else
+	RCC->APB2PCENR |= RCC_APB2Periph_GPIOC;
 	// PC1 is SDA, 10MHz Output, alt func, open-drain
 	GPIOC->CFGLR &= ~(0xf<<(4*1));
 	GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*1);
 
 	// PC2 is SCL, 10MHz Output, alt func, open-drain
 	GPIOC->CFGLR &= ~(0xf<<(4*2));
 	GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_OD_AF)<<(4*2);
-
+#endif
+
 #ifdef IRQ_DIAG
 	// GPIO diags on PC3/PC4
 	GPIOC->CFGLR &= ~(0xf<<(4*3));