Adapt repository links within markdowns.

README.md

@@ -48,20 +48,20 @@ details below in the [Developers](#developers-welcome) section.
 
 ### Parser
 
-[Learn more about the parser implementation here](./verilog/parser).
+[Learn more about the parser implementation here](./verible/verilog/parser).
 
-We provide a standalone [`verible-verilog-syntax`](./verilog/tools/syntax) tool
+We provide a standalone [`verible-verilog-syntax`](./verible/verilog/tools/syntax) tool
 to help with visualizing the syntax structure as understood by the lexer and
 parser. This is very useful for troubleshooting and understand the internal
 representations seen by the other tools.
 
 The tool has an ability of exporting a concrete syntax tree in JSON format,
 making use of it in external tools easy. There is also a
-[Python wrapper module and a few example scripts](./verilog/tools/syntax/export_json_examples).
+[Python wrapper module and a few example scripts](./verible/verilog/tools/syntax/export_json_examples).
 
 ### Style Linter
 
-[`verible-verilog-lint`](./verilog/tools/lint) identifies constructs or patterns
+[`verible-verilog-lint`](./verible/verilog/tools/lint) identifies constructs or patterns
 in code that are deemed undesirable according to a style guide. The main goal is
 to relieve humans the burden of reviewing code for style compliance. Many
 [lint rules][lint-rule-list] use syntax tree pattern matching to find style
@@ -78,12 +78,12 @@ Features:
 
 Documentation:
 
-*   [Style linter user documentation](./verilog/tools/lint)
+*   [Style linter user documentation](./verible/verilog/tools/lint)
 *   [Generated lint rule documentation][lint-rule-list]
 
 ### Formatter
 
-The [`verible-verilog-format`](./verilog/tools/formatter) formatter manages
+The [`verible-verilog-format`](./verible/verilog/tools/formatter) formatter manages
 whitespace in accordance with a particular style. The main goal is to relieve
 humans of having to manually manage whitespace, wrapping, and indentation, and
 to provide a tool that can be integrated into any editor to enable
@@ -106,7 +106,7 @@ See https://github.com/chipsalliance/verible/issues/528
 
 ### Language Server
 
-The [`verible-verilog-ls`](./verilog/tools/ls) is a language server that
+The [`verible-verilog-ls`](./verible/verilog/tools/ls) is a language server that
 provides the functionalities that come with the Verible command line tools
 also directly in your editor.
 
@@ -120,19 +120,19 @@ provides quick-fixes
 
 ### Lexical Diff
 
-[`verible-verilog-diff`](./verilog/tools/diff) compares two input files for
+[`verible-verilog-diff`](./verible/verilog/tools/diff) compares two input files for
 equivalence.
 
 ### Verible project tool
 
-[`verible-verilog-project`](./verilog/tools/project) is a multi-tool that
+[`verible-verilog-project`](./verible/verilog/tools/project) is a multi-tool that
 operates on whole Verilog projects, consisting of a file list and related
 configurations. This serves as a diagnostic tool for analyzing (and potentially
 transforming) project-level sources.
 
 ### Code Obfuscator
 
-[`verible-verilog-obfuscate`](./verilog/tools/obfuscator) transforms Verilog
+[`verible-verilog-obfuscate`](./verible/verilog/tools/obfuscator) transforms Verilog
 code by replacing identifiers with obfuscated names of equal length, and
 preserving all other text, including spaces. Output is written to stdout. The
 resulting file size is the same as the original. This is useful for preparing
@@ -145,13 +145,13 @@ See https://github.com/chipsalliance/verible/issues/528
 
 ### Preprocessor
 
-[`verible-verilog-preprocessor`](./verilog/tools/preprocessor) is a collection
+[`verible-verilog-preprocessor`](./verible/verilog/tools/preprocessor) is a collection
 of preprocessor-like tools, (but does not include a fully-featured Verilog
 preprocessor yet.)
 
 ### Source Code Indexer
 
-[`verible-verilog-kythe-extractor`](./verilog/tools/kythe) extracts indexing
+[`verible-verilog-kythe-extractor`](./verible/verilog/tools/kythe) extracts indexing
 facts from SV source code using the [Kythe](http://kythe.io) schema, which can
 then enhance IDEs with linked cross-references for ease of source code
 navigation.

doc/development.md

@@ -28,8 +28,8 @@ To learn more about how to use Kythe to
 Each directory in the source tree contains a short README.md describing the
 contents.
 
-*   [common/](../common) contains all language-agnostic libraries and tools
-*   [verilog/](../verilog) contains Verilog-specific libraries and tools
+*   [common/](../verible/common) contains all language-agnostic libraries and tools
+*   [verilog/](../verible/verilog) contains Verilog-specific libraries and tools
 *   [external_libs/](../external_libs) contains some library dependencies
 
 ## Verilog Front-End

doc/style_lint.md

@@ -25,7 +25,7 @@ Before you begin, familiarize yourself with:
 Whose style guide serves as a reference for lint rules? Everyone and anyone's.
 Every team may set its own guidelines on what constitutes correct style. The
 style linter hosts an ever-growing library of rules, but _you_ decide
-[which rules or configurations](../verilog/tools/lint.md#usage) best suit your
+[which rules or configurations](../verible/verilog/tools/lint.md#usage) best suit your
 project.
 
 ### Traits of good lint rules
@@ -85,7 +85,7 @@ syntax trees.
 
 ### Syntax Tree Examiner
 
-Use [`verible-verilog-syntax --printtree`](../verilog/tools/syntax) to examine
+Use [`verible-verilog-syntax --printtree`](../verible/verilog/tools/syntax) to examine
 the syntax structure of examples of code of interest.
 
 ### Syntax Tree Visitors
@@ -96,7 +96,7 @@ to query the stack to determine the context at any node.
 
 ### Syntax Tree Direct Substructure Access
 
-The [SV concrete syntax tree (CST) is described here](../verilog/CST). The CST
+The [SV concrete syntax tree (CST) is described here](../verible/verilog/CST). The CST
 library contains a number of useful `GetXFromY`-type accessor functions. These
 functions offer the most direct way of extracting information from syntax tree
 nodes. Accessor functions are useful when you've already narrowed down your
@@ -152,7 +152,7 @@ Cons:
 
 ### Single Node Type Matchers
 
-For every [SystemVerilog CST node enum](../verilog/CST/verilog_nonterminals.h),
+For every [SystemVerilog CST node enum](../verible/verilog/CST/verilog_nonterminals.h),
 we produce a corresponding node-matcher in [verilog_matchers.h] that finds that
 node type. For example, `NodekFunctionDeclaration` matches nodes tagged
 `kFunctionDeclaration`. These are defined using [TagMatchBuilder].
@@ -192,7 +192,7 @@ match result; they are fully commutative.
 Many matchers support _binding_ to user-provided names called
 [BindableMatchers]. This lets you save interesting subtree positions found
 during the match and retrieve them from a [BoundSymbolManager].
-[Example using `.Bind()`](../verilog/analysis/checkers/undersized_binary_literal_rule.h).
+[Example using `.Bind()`](../verible/verilog/analysis/checkers/undersized_binary_literal_rule.h).
 
 ## Reporting Positive Findings