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linter: Add suspicious-semicolon rule
Inspired by clang-tidy's similar check. Things to note: verilog/tools/lint/testdata/forbid_consecutive_null_statement.sv has been modified so it doesn't fail under this rule too.
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// Copyright 2017-2023 The Verible Authors. | ||
// | ||
// Licensed under the Apache License, Version 2.0 (the "License"); | ||
// you may not use this file except in compliance with the License. | ||
// You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
// Unless required by applicable law or agreed to in writing, software | ||
// distributed under the License is distributed on an "AS IS" BASIS, | ||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
// See the License for the specific language governing permissions and | ||
// limitations under the License. | ||
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#include "suspicious_semicolon_rule.h" | ||
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#include "common/analysis/matcher/matcher.h" | ||
#include "verilog/CST/verilog_matchers.h" | ||
#include "verilog/CST/verilog_nonterminals.h" | ||
#include "verilog/analysis/lint_rule_registry.h" | ||
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namespace verilog { | ||
namespace analysis { | ||
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using verible::matcher::Matcher; | ||
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VERILOG_REGISTER_LINT_RULE(SuspiciousSemicolon); | ||
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static constexpr absl::string_view kMessage = | ||
"Potentially unintended semicolon"; | ||
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const LintRuleDescriptor &SuspiciousSemicolon::GetDescriptor() { | ||
static const LintRuleDescriptor d{ | ||
.name = "suspicious-semicolon", | ||
.topic = "bugprone", | ||
.desc = | ||
"Checks that there are no suspicious semicolons that might affect " | ||
"code behaviour but escape quick visual inspection"}; | ||
return d; | ||
} | ||
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static const Matcher &NullStatementMatcher() { | ||
static const Matcher matcher(NodekNullStatement()); | ||
return matcher; | ||
} | ||
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void SuspiciousSemicolon::HandleNode( | ||
const verible::SyntaxTreeNode &node, | ||
const verible::SyntaxTreeContext &context) { | ||
verible::matcher::BoundSymbolManager manager; | ||
if (!NullStatementMatcher().Matches(node, &manager)) return; | ||
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// Waive @(posedge clk); | ||
// But catch always_ff @(posedge clk); | ||
const bool parent_is_proc_timing_ctrl_statement = | ||
context.DirectParentIs(NodeEnum::kProceduralTimingControlStatement); | ||
if (!context.IsInside(NodeEnum::kAlwaysStatement) && | ||
parent_is_proc_timing_ctrl_statement) { | ||
return; | ||
} | ||
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if (!parent_is_proc_timing_ctrl_statement && | ||
!context.DirectParentIsOneOf( | ||
{NodeEnum::kForeachLoopStatement, NodeEnum::kWhileLoopStatement, | ||
NodeEnum::kForLoopStatement, NodeEnum::kForeverLoopStatement, | ||
NodeEnum::kIfBody, NodeEnum::kElseBody})) { | ||
return; | ||
} | ||
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violations_.insert(verible::LintViolation( | ||
node, kMessage, context, | ||
{verible::AutoFix("Remove ';'", | ||
{verible::StringSpanOfSymbol(node), ""})})); | ||
} | ||
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verible::LintRuleStatus SuspiciousSemicolon::Report() const { | ||
return verible::LintRuleStatus(violations_, GetDescriptor()); | ||
} | ||
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} // namespace analysis | ||
} // namespace verilog |
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// Copyright 2017-2023 The Verible Authors. | ||
// | ||
// Licensed under the Apache License, Version 2.0 (the "License"); | ||
// you may not use this file except in compliance with the License. | ||
// You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
// Unless required by applicable law or agreed to in writing, software | ||
// distributed under the License is distributed on an "AS IS" BASIS, | ||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
// See the License for the specific language governing permissions and | ||
// limitations under the License. | ||
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#ifndef VERIBLE_VERILOG_ANALYSIS_CHECKERS_SUSPICIOUS_SEMICOLON_H_ | ||
#define VERIBLE_VERILOG_ANALYSIS_CHECKERS_SUSPICIOUS_SEMICOLON_H_ | ||
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#include "common/analysis/lint_rule_status.h" | ||
#include "common/analysis/syntax_tree_lint_rule.h" | ||
#include "verilog/analysis/descriptions.h" | ||
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namespace verilog { | ||
namespace analysis { | ||
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/* | ||
* Detect suspicious semicolons. Inspired by clang-tidy's | ||
* bugprone-suspicious-semicolon check. | ||
* | ||
* This rule detects extra semicolons that modify code behaviour | ||
* while having a good chance to escape quick visual inspection. | ||
* | ||
* A couple of examples: | ||
* | ||
* if (condition); | ||
* `uvm_fatal(...); | ||
* | ||
* while (condition); begin | ||
* doSomething(); | ||
* end | ||
* | ||
* Reference: | ||
* https://clang.llvm.org/extra/clang-tidy/checks/bugprone/suspicious-semicolon.html#bugprone-suspicious-semicolon | ||
*/ | ||
class SuspiciousSemicolon : public verible::SyntaxTreeLintRule { | ||
public: | ||
using rule_type = verible::SyntaxTreeLintRule; | ||
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static const LintRuleDescriptor &GetDescriptor(); | ||
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void HandleNode(const verible::SyntaxTreeNode &node, | ||
const verible::SyntaxTreeContext &context) final; | ||
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verible::LintRuleStatus Report() const final; | ||
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private: | ||
std::set<verible::LintViolation> violations_; | ||
}; | ||
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} // namespace analysis | ||
} // namespace verilog | ||
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#endif // VERIBLE_VERILOG_ANALYSIS_CHECKERS_SUSPICIOUS_SEMICOLON_H_ |
81 changes: 81 additions & 0 deletions
81
verilog/analysis/checkers/suspicious_semicolon_rule_test.cc
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// Copyright 2017-2023 The Verible Authors. | ||
// | ||
// Licensed under the Apache License, Version 2.0 (the "License"); | ||
// you may not use this file except in compliance with the License. | ||
// You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
// Unless required by applicable law or agreed to in writing, software | ||
// distributed under the License is distributed on an "AS IS" BASIS, | ||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
// See the License for the specific language governing permissions and | ||
// limitations under the License. | ||
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#include "verilog/analysis/checkers/suspicious_semicolon_rule.h" | ||
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#include "common/analysis/syntax_tree_linter_test_utils.h" | ||
#include "verilog/analysis/verilog_analyzer.h" | ||
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namespace verilog { | ||
namespace analysis { | ||
namespace { | ||
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static constexpr int kToken = ';'; | ||
TEST(SuspiciousSemicolon, DetectSuspiciousSemicolons) { | ||
const std::initializer_list<verible::LintTestCase> | ||
kSuspiciousSemicolonTestCases = { | ||
{"module m; initial begin if(x)", {kToken, ";"}, " end endmodule"}, | ||
{"module m; initial begin if(x) x; else", | ||
{kToken, ";"}, | ||
" y; end endmodule"}, | ||
{"module m; initial begin while(x)", {kToken, ";"}, " end endmodule"}, | ||
{"module m; initial begin forever", {kToken, ";"}, " end endmodule"}, | ||
{"module m; always_ff @(posedge clk)", {kToken, ";"}, " endmodule"}, | ||
{"module m; initial begin foreach (array[i])", | ||
{kToken, ";"}, | ||
" end endmodule"}, | ||
}; | ||
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verible::RunLintTestCases<VerilogAnalyzer, SuspiciousSemicolon>( | ||
kSuspiciousSemicolonTestCases); | ||
} | ||
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TEST(SuspiciousSemicolon, ShouldNotComplain) { | ||
const std::initializer_list<verible::LintTestCase> | ||
kSuspiciousSemicolonTestCases = { | ||
{""}, | ||
{"module m; initial begin if(x) begin end end endmodule"}, | ||
{"module m; @(posedge clk); endmodule"}, | ||
{"module m; always_ff @(posedge clk) begin ; end endmodule"}, | ||
{"class c; int x;; endclass"}, | ||
}; | ||
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verible::RunLintTestCases<VerilogAnalyzer, SuspiciousSemicolon>( | ||
kSuspiciousSemicolonTestCases); | ||
} | ||
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TEST(SuspiciousSemicolon, ApplyAutoFix) { | ||
const std::initializer_list<verible::AutoFixInOut> | ||
kSuspiciousSemicolonTestCases = { | ||
{"module m; initial begin if(x); end endmodule", | ||
"module m; initial begin if(x) end endmodule"}, | ||
{"module m; initial begin if(x) x; else; y; end endmodule", | ||
"module m; initial begin if(x) x; else y; end endmodule"}, | ||
{"module m; initial begin while(x); end endmodule", | ||
"module m; initial begin while(x) end endmodule"}, | ||
{"module m; initial begin forever; end endmodule", | ||
"module m; initial begin forever end endmodule"}, | ||
{"module m; always_ff @(posedge clk); endmodule", | ||
"module m; always_ff @(posedge clk) endmodule"}, | ||
{"module m; initial begin foreach (array[i]); end endmodule", | ||
"module m; initial begin foreach (array[i]) end endmodule"}, | ||
}; | ||
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verible::RunApplyFixCases<VerilogAnalyzer, SuspiciousSemicolon>( | ||
kSuspiciousSemicolonTestCases); | ||
} | ||
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} // namespace | ||
} // namespace analysis | ||
} // namespace verilog |
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1 change: 0 additions & 1 deletion
1
verilog/tools/lint/testdata/forbid_consecutive_null_statements.sv
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@@ -1,4 +1,3 @@ | ||
module forbid_consecutive_null_statements; | ||
always_ff @(posedge foo) | ||
;; // [Style: consecutive-null-statements] [forbid-consecutive-null-statements] | ||
endmodule |
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module suspicious_semicolon (); | ||
initial begin | ||
if (x); | ||
$display("Hi"); | ||
end | ||
endmodule |