Merge pull request #1464 from hzeller/20220916-provide-append-fun-for…

…-file-list

Provide a FileList::Append() method to concatenate.

verilog/analysis/BUILD

@@ -359,9 +359,19 @@ cc_test(
 
 cc_library(
     name = "verilog_filelist",
+    srcs = ["verilog_filelist.cc"],
     hdrs = ["verilog_filelist.h"],
 )
 
+cc_test(
+    name = "verilog_filelist_test",
+    srcs = ["verilog_filelist_test.cc"],
+    deps = [
+        ":verilog_filelist",
+        "@com_google_googletest//:gtest_main",
+    ],
+)
+
 cc_library(
     name = "verilog_project",
     srcs = ["verilog_project.cc"],

verilog/analysis/verilog_filelist.cc

@@ -0,0 +1,26 @@
+// Copyright 2022 The Verible Authors.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "verilog/analysis/verilog_filelist.h"
+
+void verilog::FileList::Append(const FileList &other) {
+  file_paths.insert(file_paths.end(), other.file_paths.begin(),
+                    other.file_paths.end());
+  preprocessing.include_dirs.insert(preprocessing.include_dirs.end(),
+                                    other.preprocessing.include_dirs.begin(),
+                                    other.preprocessing.include_dirs.end());
+  preprocessing.defines.insert(preprocessing.defines.end(),
+                               other.preprocessing.defines.begin(),
+                               other.preprocessing.defines.end());
+}

verilog/analysis/verilog_filelist.h

@@ -32,20 +32,39 @@ struct TextMacroDefinition {
 };
 
 // File list for compiling a System Verilog project.
+// TODO: ideally, all the strings would be string_views, but we need to make
+//       sure to have the relevant backing store live.
+// TODO: are there cases in which files and incdirs are interleaved so that
+//       the first files don't see all the incdirs yet, but after more incdirs
+//       are added, all of them are relevant ? If so, this would require some
+//       restructering.
+// TODO: document if files are relative to tool invocation or relative to
+//       file_list_path (the latter makes more sense, but I think currently that
+//       is underspecified).
+// TODO: Alongside previous: also introduce file_list_root field ?
 struct FileList {
   // A struct holding information relevant to "VerilogPreprocess" preprocessor.
   struct PreprocessingInfo {
     // Directories where to search for the included files.
     std::vector<std::string> include_dirs;
+
     // Defined macros.
     std::vector<TextMacroDefinition> defines;
   };
-  // Ordered list of files to compile.
-  std::vector<std::string> file_paths;
+
   // Path to the file list.
   std::string file_list_path;
+
+  // Ordered list of files to compile.
+  std::vector<std::string> file_paths;
+
   // Information relevant to the preprocessor.
   PreprocessingInfo preprocessing;
+
+  // Merge other file list into this one, essentially concatenating all
+  // vectors of information at the end.
+  // Modifies this FileList except "file_list_path", which is left untouched.
+  void Append(const FileList& other);
 };
 
 }  // namespace verilog

verilog/analysis/verilog_filelist_test.cc

@@ -0,0 +1,45 @@
+// Copyright 2022 The Verible Authors.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "verilog/analysis/verilog_filelist.h"
+
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
+
+using testing::ElementsAre;
+
+namespace verilog {
+
+TEST(FileListTest, Append) {
+  FileList a;
+  a.file_list_path = "path A";
+  a.file_paths = {"file1.sv", "file2.sv"};
+  a.preprocessing.include_dirs = {"foo", "bar"};
+  a.preprocessing.defines = {{"DEBUG", "1"}, {"A", "B"}};
+
+  FileList b;
+  b.file_list_path = "path B";
+  b.file_paths = {"file3.sv"};
+  b.preprocessing.include_dirs = {"baz"};
+  b.preprocessing.defines = {{"C", "D"}};
+
+  a.Append(b);
+
+  EXPECT_EQ(a.file_list_path, "path A");  // not modified
+  EXPECT_THAT(a.file_paths, ElementsAre("file1.sv", "file2.sv", "file3.sv"));
+  EXPECT_THAT(a.preprocessing.include_dirs, ElementsAre("foo", "bar", "baz"));
+  EXPECT_EQ(a.preprocessing.defines.size(), 3);
+}
+
+}  // namespace verilog