Merge pull request #683 from hzeller/fix-dependencies

Remove superfluous, add missing dependencies in BUILD files.
chipsalliance · Feb 20, 2021 · c1a388a · c1a388a
2 parents f698155 + f009c20
commit c1a388a
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/verilog/CST/BUILD b/verilog/CST/BUILD
@@ -906,7 +906,6 @@ cc_library(
         "//common/text:symbol",
         "//common/text:token_info",
         "//common/text:token_info_json",
-        "//common/text:tree_utils",
         "//common/util:value_saver",
         "//verilog/parser:verilog_token",
         "@com_google_absl//absl/strings",
@@ -959,7 +958,6 @@ cc_test(
         "//common/text:symbol",
         "//common/util:logging",
         "//verilog/analysis:verilog_analyzer",
-        "@com_google_absl//absl/memory",
         "@com_google_absl//absl/strings",
         "@com_google_googletest//:gtest_main",
         "@jsoncpp_git//:jsoncpp",

diff --git a/verilog/tools/syntax/export_json_examples/BUILD b/verilog/tools/syntax/export_json_examples/BUILD
@@ -32,7 +32,10 @@ py_binary(
     srcs_version = "PY3",
     python_version = "PY3",
     main = "print_modules.py",
-    deps = [":verible_verilog_syntax_py"],
+    deps = [
+         ":verible_verilog_syntax_py",
+         "@python_anytree//:anytree",
+    ],
     data = ["//verilog/tools/syntax:verible-verilog-syntax"],
     args = ["$(location //verilog/tools/syntax:verible-verilog-syntax)"],
 )
@@ -43,7 +46,10 @@ py_binary(
     srcs_version = "PY3",
     python_version = "PY3",
     main = "print_tree.py",
-    deps = [":verible_verilog_syntax_py"],
+    deps = [
+         ":verible_verilog_syntax_py",
+         "@python_anytree//:anytree",
+    ],
     data = ["//verilog/tools/syntax:verible-verilog-syntax"],
     args = ["$(location //verilog/tools/syntax:verible-verilog-syntax)"],
 )