verilog: analysis: checkers: Update always_comb_rule

Signed-off-by: Mateusz Sierszulski <[email protected]>
chipsalliance · Feb 15, 2023 · a108c4c · a108c4c
1 parent ed187c5
commit a108c4c
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diff --git a/verilog/analysis/checkers/always_comb_rule.cc b/verilog/analysis/checkers/always_comb_rule.cc
@@ -63,13 +63,22 @@ static const Matcher& AlwaysStarMatcher() {
   return matcher;
 }
 
+static const Matcher& AlwaysStarMatcherWithParentheses() {
+  static const Matcher matcher(NodekAlwaysStatement(
+      AlwaysKeyword(), AlwaysStatementHasEventControlStarAndParentheses()));
+  return matcher;
+}
+
 void AlwaysCombRule::HandleSymbol(const verible::Symbol& symbol,
                                   const SyntaxTreeContext& context) {
   // Check for offending use of always @*
   verible::matcher::BoundSymbolManager manager;
   if (AlwaysStarMatcher().Matches(symbol, &manager)) {
     violations_.insert(LintViolation(symbol, kMessage, context));
   }
+  if (AlwaysStarMatcherWithParentheses().Matches(symbol, &manager)) {
+    violations_.insert(LintViolation(symbol, kMessage, context));
+  }
 }
 
 LintRuleStatus AlwaysCombRule::Report() const {

diff --git a/verilog/analysis/checkers/always_comb_rule_test.cc b/verilog/analysis/checkers/always_comb_rule_test.cc
@@ -40,6 +40,14 @@ TEST(AlwaysCombTest, FunctionFailures) {
       {"module m;\ninitial begin end\nendmodule"},
       {"module m;\n", {kToken, "always"}, " @* begin end\nendmodule"},
       {"module m;\n", {kToken, "always"}, " @(*) begin end\nendmodule"},
+      {"module m;\n", {kToken, "always"}, " @( *) begin end\nendmodule"},
+      {"module m;\n", {kToken, "always"}, " @(* ) begin end\nendmodule"},
+      {"module m;\n", {kToken, "always"}, " @( * ) begin end\nendmodule"},
+      {"module m;\n", {kToken, "always"}, " @(/*t*/*) begin end\nendmodule"},
+      {"module m;\n", {kToken, "always"}, " @(*/*t*/) begin end\nendmodule"},
+      {"module m;\n",
+       {kToken, "always"},
+       " @(/*t*/*/*t*/) begin end\nendmodule"},
       {"module m;\nalways_ff begin a <= b; end\nendmodule"},
       {"module m;\nalways_comb begin a = b; end\nendmodule"},
   };