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Use the right unsigned type for a loop through a vector.
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PiperOrigin-RevId: 297470821
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hzeller committed Feb 27, 2020
1 parent c0dce5a commit 834d8f9
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions verilog/analysis/verilog_equivalence_test.cc
Original file line number Diff line number Diff line change
Expand Up @@ -58,8 +58,8 @@ TEST(FormatEquivalentTest, Spaces) {
"\n",
"\t",
};
for (int i = 0; i < kTestCases.size(); ++i) {
for (int j = i + 1; j < kTestCases.size(); ++j) {
for (size_t i = 0; i < kTestCases.size(); ++i) {
for (size_t j = i + 1; j < kTestCases.size(); ++j) {
ExpectCompareWithErrstream(FormatEquivalent, true, kTestCases[i],
kTestCases[j]);
}
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