Bundle definition

.gitignore

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+/out/
+/.idea/
+/.bsp/

tilelink/src/bundle/MessageTypes.scala

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+// SPDX-License-Identifier: Apache-2.0
+
+package org.chipsalliance.tilelink
+package bundle
+
+import chisel3._
+import chisel3.internal.firrtl.Width
+
+/** opcode field of TileLink messages
+  *
+  * cf. TileLink Spec 1.9.3 Table 12
+  */
+object OpCode {
+  protected[tilelink] val width: Width = 3.W
+
+  val PutFullData:    UInt = 0.U(width)
+  val PutPartialData: UInt = 1.U(width)
+  val ArithmeticData: UInt = 2.U(width)
+  val LogicalData:    UInt = 3.U(width)
+  val Get:            UInt = 4.U(width)
+  val Intent:         UInt = 5.U(width)
+  val AcquireBlock:   UInt = 6.U(width)
+  val AcquirePerm:    UInt = 7.U(width)
+  val ProbePerm:      UInt = 7.U(width)
+  val AccessAck:      UInt = 0.U(width)
+  val AccessAckData:  UInt = 1.U(width)
+  val HintAck:        UInt = 2.U(width)
+  val ProbeAck:       UInt = 4.U(width)
+  val ProbeAckData:   UInt = 5.U(width)
+  val Release:        UInt = 6.U(width)
+  val ReleaseData:    UInt = 7.U(width)
+  val Grant:          UInt = 4.U(width)
+  val GrantData:      UInt = 5.U(width)
+  val ProbeBlock:     UInt = 6.U(width)
+  val ReleaseAck:     UInt = 6.U(width)
+  // GrantAck has no Opcode
+}
+
+/** param field of TileLink messages
+  *
+  * Allowed values are dependent on opcode of the message.
+  */
+object Param {
+  protected[tilelink] val width: Width = 3.W
+
+  /** Reserved param fields (e.g. a_param in Get message) should be tied to zero
+    */
+  def tieZero: UInt = 0.U(width)
+
+  /** param field for ArithmeticData
+    * TileLink Spec 1.9.3 Table 23
+    */
+  object Arithmetic {
+    val MIN:  UInt = 0.U(width)
+    val MAX:  UInt = 1.U(width)
+    val MINU: UInt = 2.U(width)
+    val MAXU: UInt = 3.U(width)
+    val ADD:  UInt = 4.U(width)
+  }
+
+  /** param field for LogicalData
+    * TileLink Spec 1.9.3 Table 25
+    */
+  object Logical {
+    val XOR:  UInt = 0.U(width)
+    val OR:   UInt = 1.U(width)
+    val AND:  UInt = 2.U(width)
+    val SWAP: UInt = 3.U(width)
+  }
+
+  /** param field for Intent
+    * TileLink Spec 1.9.3 Table 27
+    */
+  object Intent {
+    val PrefetchRead:  UInt = 0.U(width)
+    val PrefetchWrite: UInt = 1.U(width)
+    val CBOInval:      UInt = 5.U(width)
+    val CBOClean:      UInt = 6.U(width)
+    val CBOFlush:      UInt = 7.U(width)
+  }
+
+  /** permissions transitions encodings for Cap
+    * TileLink Spec 1.9.3 Table 31
+    */
+  object Cap {
+    val toT: UInt = 0.U(width)
+    val toB: UInt = 1.U(width)
+    val toN: UInt = 2.U(width)
+  }
+
+  /** permissions transitions encodings for Grow
+    * TileLink Spec 1.9.3 Table 31
+    */
+  object Grow {
+    val NtoB: UInt = 0.U(width)
+    val NtoT: UInt = 1.U(width)
+    val BtoT: UInt = 2.U(width)
+  }
+
+  /** permissions transitions encodings for Prune
+    * TileLink Spec 1.9.3 Table 31
+    */
+  object Prune {
+    val TtoB: UInt = 0.U(width)
+    val TtoN: UInt = 1.U(width)
+    val BtoN: UInt = 2.U(width)
+  }
+
+  /** permissions transitions encodings for Report
+    * TileLink Spec 1.9.3 Table 31
+    */
+  object Report {
+    val TtoT: UInt = 3.U(width)
+    val BtoB: UInt = 4.U(width)
+    val NtoN: UInt = 5.U(width)
+  }
+}

tilelink/src/bundle/NoTLCException.scala

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+// SPDX-License-Identifier: Apache-2.0
+
+package org.chipsalliance.tilelink
+package bundle
+
+import chisel3.ChiselException
+private class NoTLCException(
+  channel:       String,
+  linkParameter: TLLinkParameter)
+    extends ChiselException(
+      s"call $channel in TLLink is not present in a TL-UL or TL-UH bus:\n $linkParameter"
+    )

tilelink/src/bundle/TLChannel.scala

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+// SPDX-License-Identifier: Apache-2.0
+
+package org.chipsalliance.tilelink
+package bundle
+
+import chisel3._
+
+trait TLChannel extends Bundle {
+  val parameter: TLChannelParameter
+}
+
+class TLChannelA(val parameter: TileLinkChannelAParameter) extends TLChannel {
+  private val maskWidth = parameter.dataWidth / 8
+  // NOTE: this field is called a_code in TileLink spec version 1.9.3 p. 16, which is probably a typo
+  val opcode:  UInt = UInt(OpCode.width)
+  val param:   UInt = UInt(Param.width)
+  val size:    UInt = UInt(parameter.sizeWidth.W)
+  val source:  UInt = UInt(parameter.sourceWidth.W)
+  val address: UInt = UInt(parameter.addressWidth.W)
+  val mask:    UInt = UInt(maskWidth.W)
+  val data:    UInt = UInt(parameter.dataWidth.W)
+  val corrupt: Bool = Bool()
+}
+
+class TLChannelB(val parameter: TileLinkChannelBParameter) extends TLChannel {
+  private val maskWidth = parameter.dataWidth / 8
+  val opcode:  UInt = UInt(OpCode.width)
+  val param:   UInt = UInt(Param.width)
+  val size:    UInt = UInt(parameter.sizeWidth.W)
+  val source:  UInt = UInt(parameter.sourceWidth.W)
+  val address: UInt = UInt(parameter.addressWidth.W)
+  val mask:    UInt = UInt(maskWidth.W)
+  val data:    UInt = UInt(parameter.dataWidth.W)
+  val corrupt: Bool = Bool()
+}
+
+class TLChannelC(val parameter: TileLinkChannelCParameter) extends TLChannel {
+  val opcode:  UInt = UInt(OpCode.width)
+  val param:   UInt = UInt(Param.width)
+  val size:    UInt = UInt(parameter.sizeWidth.W)
+  val source:  UInt = UInt(parameter.sourceWidth.W)
+  val address: UInt = UInt(parameter.addressWidth.W)
+  val data:    UInt = UInt(parameter.dataWidth.W)
+  val corrupt: Bool = Bool()
+}
+
+class TLChannelD(val parameter: TileLinkChannelDParameter) extends TLChannel {
+  val opcode:  UInt = UInt(OpCode.width)
+  val param:   UInt = UInt(Param.width)
+  val size:    UInt = UInt(parameter.sizeWidth.W)
+  val source:  UInt = UInt(parameter.sourceWidth.W)
+  val sink:    UInt = UInt(parameter.sinkWidth.W)
+  val denied:  Bool = Bool()
+  val data:    UInt = UInt(parameter.dataWidth.W)
+  val corrupt: Bool = Bool()
+}
+
+class TLChannelE(val parameter: TileLinkChannelEParameter) extends TLChannel {
+  val sink: UInt = UInt(parameter.sinkWidth.W)
+}

tilelink/src/bundle/TLChannelParameter.scala

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+// SPDX-License-Identifier: Apache-2.0
+
+package org.chipsalliance.tilelink
+package bundle
+
+import chisel3.util.isPow2
+
+import upickle.default.{macroRW, ReadWriter => RW}
+
+sealed trait TLChannelParameter
+
+object TLChannelParameter        {
+  implicit val rw: RW[TLChannelParameter] = RW.merge(
+    TileLinkChannelAParameter.rw,
+    TileLinkChannelBParameter.rw,
+    TileLinkChannelCParameter.rw,
+    TileLinkChannelDParameter.rw,
+    TileLinkChannelEParameter.rw
+  )
+
+  def bundle(p: TLChannelParameter): TLChannel = {
+    p match {
+      case a: TileLinkChannelAParameter => new TLChannelA(a)
+      case b: TileLinkChannelBParameter => new TLChannelB(b)
+      case c: TileLinkChannelCParameter => new TLChannelC(c)
+      case d: TileLinkChannelDParameter => new TLChannelD(d)
+      case e: TileLinkChannelEParameter => new TLChannelE(e)
+    }
+  }
+}
+
+case class TileLinkChannelAParameter(
+  addressWidth: Int,
+  sourceWidth:  Int,
+  dataWidth:    Int,
+  sizeWidth:    Int)
+    extends TLChannelParameter {
+  require(addressWidth > 0)
+  require(sourceWidth > 0)
+  require(dataWidth > 0)
+  require(sizeWidth > 0)
+  require(dataWidth % 8 == 0, "Width of data field must be multiples of 8")
+  require(
+    isPow2(dataWidth / 8),
+    "Width of data field in bytes must be power of 2"
+  )
+}
+object TileLinkChannelAParameter {
+  implicit val rw: RW[TileLinkChannelAParameter] = macroRW
+}
+
+case class TileLinkChannelBParameter(
+  addressWidth: Int,
+  sourceWidth:  Int,
+  dataWidth:    Int,
+  sizeWidth:    Int)
+    extends TLChannelParameter {
+  require(addressWidth > 0)
+  require(sourceWidth > 0)
+  require(dataWidth > 0)
+  require(sizeWidth > 0)
+  require(dataWidth % 8 == 0, "Width of data field must be multiples of 8")
+  require(
+    isPow2(dataWidth / 8),
+    "Width of data field in bytes must be power of 2"
+  )
+}
+object TileLinkChannelBParameter {
+  implicit val rw: RW[TileLinkChannelBParameter] = macroRW
+}
+
+case class TileLinkChannelCParameter(
+  addressWidth: Int,
+  sourceWidth:  Int,
+  dataWidth:    Int,
+  sizeWidth:    Int)
+    extends TLChannelParameter {
+  require(addressWidth > 0)
+  require(sourceWidth > 0)
+  require(dataWidth > 0)
+  require(sizeWidth > 0)
+  require(dataWidth % 8 == 0, "Width of data field must be multiples of 8")
+  require(
+    isPow2(dataWidth / 8),
+    "Width of data field in bytes must be power of 2"
+  )
+}
+object TileLinkChannelCParameter {
+  implicit val rw: RW[TileLinkChannelCParameter] = macroRW
+}
+
+case class TileLinkChannelDParameter(
+  sourceWidth: Int,
+  sinkWidth:   Int,
+  dataWidth:   Int,
+  sizeWidth:   Int)
+    extends TLChannelParameter {
+  require(sourceWidth > 0)
+  require(sinkWidth > 0)
+  require(dataWidth > 0)
+  require(sizeWidth > 0)
+  require(dataWidth % 8 == 0, "Width of data field must be multiples of 8")
+  require(
+    isPow2(dataWidth / 8),
+    "Width of data field in bytes must be power of 2"
+  )
+}
+object TileLinkChannelDParameter {
+  implicit val rw: RW[TileLinkChannelDParameter] = macroRW
+}
+
+case class TileLinkChannelEParameter(sinkWidth: Int) extends TLChannelParameter {
+  require(sinkWidth > 0)
+}
+object TileLinkChannelEParameter {
+  implicit val rw: RW[TileLinkChannelEParameter] = macroRW
+}