timing debug

omreaderlib/src/T1OMReaderAPI.scala

@@ -54,7 +54,7 @@ object Path {
   implicit val rw:        ReadWriter[Instruction] = macroRW
   def parse(str: String): Path                    =
     str match {
-      case s"OMInstanceTarget:~${top}|${hier}>${local}" =>
+      case s"OMReferenceTarget:~${top}|${hier}>${local}" =>
         Path(
           top,
           hier
@@ -65,7 +65,7 @@ object Path {
             }),
           Some(local)
         )
-      case s"OMInstanceTarget:~${top}|${hier}"          =>
+      case s"OMInstanceTarget:~${top}|${hier}"           =>
         Path(
           top,
           hier

omreaderlib/src/t1/T1.scala

@@ -18,6 +18,20 @@ class T1(val mlirbc: Array[Byte]) extends T1OMReaderAPI {
   def instructions: Seq[Instruction]                  = t1("decoder").obj("instructions").list.elements().map(_.obj).map(getInstruction)
   def sram:         Seq[SRAM]                         =
     t1("lanes").list.elements().map(_.obj("vrf").obj).flatMap(getSRAM)
-  def retime:       Seq[Retime]                       =
+
+  def permutation: Seq[Retime] = {
+    val permutation  = t1("permutation")
+    val reduceUnit   = permutation.obj("reduceUnit").obj
+    val compressUnit = permutation.obj("compress").obj
+    // TODO: need fieldOpt(name: String)
+    val floatAdder   =
+      Option.when(reduceUnit.fieldNames().contains("floatAdder"))(reduceUnit("floatAdder").obj)
+
+    (Seq(compressUnit) ++ floatAdder).flatMap(getRetime)
+  }
+
+  def vfus: Seq[Retime] =
     t1("lanes").list.elements().map(_.obj("vfus")).flatMap(_.list.elements().map(_.obj)).flatMap(getRetime)
+
+  def retime = (vfus ++ permutation).distinct
 }

omreaderlib/src/t1rocketv/T1RocketTile.scala

@@ -20,8 +20,21 @@ class T1RocketTile(val mlirbc: Array[Byte]) extends T1OMReaderAPI {
     t1("lanes").list.elements().map(_.obj("vrf").obj).flatMap(getSRAM)
   def cache:        Seq[SRAM]                         =
     Seq(tile("frontend").obj("icache").obj, tile("hellaCache").obj).flatMap(getSRAM)
-  def vfu:          Seq[Retime]                       =
+
+  def permutation: Seq[Retime] = {
+    val permutation  = t1("permutation")
+    val reduceUnit   = permutation.obj("reduceUnit").obj
+    val compressUnit = permutation.obj("compress").obj
+    // TODO: need fieldOpt(name: String)
+    val floatAdder   =
+      Option.when(reduceUnit.fieldNames().contains("floatAdder"))(reduceUnit("floatAdder").obj)
+
+    (Seq(compressUnit) ++ floatAdder).flatMap(getRetime)
+  }
+
+  def vfus: Seq[Retime] =
     t1("lanes").list.elements().map(_.obj("vfus")).flatMap(_.list.elements().map(_.obj)).flatMap(getRetime)
-  def retime = vfu
+
+  def retime = (vfus ++ permutation).distinct
   def sram   = vrf ++ cache
 }

t1/src/Bundles.scala

@@ -138,6 +138,8 @@ class LaneRequest(param: LaneParameter) extends Bundle {
   /** data of rs1 */
   val readFromScalar: UInt = UInt(param.datapathWidth.W)
 
+  val csrInterface: CSRInterface = new CSRInterface(param.vlMaxBits)
+
   // vmacc 的vd需要跨lane读 TODO: move to [[V]]
   def ma: Bool =
     decodeResult(Decoder.multiplier) && decodeResult(Decoder.uop)(1, 0).xorR && !decodeResult(Decoder.vwmacc)
@@ -220,10 +222,6 @@ class InstructionControlRecord(param: LaneParameter) extends Bundle {
   /** Store request from [[T1]]. */
   val laneRequest: LaneRequest = new LaneRequest(param)
 
-  /** csr follows the instruction. TODO: move to [[laneRequest]]
-    */
-  val csr: CSRInterface = new CSRInterface(param.vlMaxBits)
-
   /** which group is the last group for instruction. */
   val lastGroupForInstruction: UInt = UInt(param.groupNumberBits.W)
 
@@ -362,9 +360,9 @@ class LaneResponseFeedback(param: LaneParameter) extends Bundle {
   val complete: Bool = Bool()
 }
 
-class V0Update(param: LaneParameter) extends Bundle {
-  val data:   UInt = UInt(param.datapathWidth.W)
-  val offset: UInt = UInt(param.vrfOffsetBits.W)
+class V0Update(datapathWidth: Int, vrfOffsetBits: Int) extends Bundle {
+  val data:   UInt = UInt(datapathWidth.W)
+  val offset: UInt = UInt(vrfOffsetBits.W)
   // mask/ld类型的有可能不会写完整的32bit
   val mask:   UInt = UInt(4.W)
 }
@@ -794,6 +792,5 @@ class MaskUnitReadVs1(parameter: T1Parameter) extends Bundle {
 }
 
 class LaneTokenBundle extends Bundle {
-  val maskResponseRelease: Bool = Output(Bool())
-  val maskRequestRelease:  Bool = Input(Bool())
+  val maskRequestRelease: Bool = Input(Bool())
 }

t1/src/FloatModule.scala

@@ -17,7 +17,7 @@ object FloatAdderParameter {
   implicit def rwP = upickle.default.macroRW[FloatAdderParameter]
 }
 
-case class FloatAdderParameter(expWidth: Int, sigWidth: Int) extends SerializableModuleParameter
+case class FloatAdderParameter(expWidth: Int, sigWidth: Int, latency: Int) extends SerializableModuleParameter
 
 class FloatAdderInterface(val parameter: FloatAdderParameter) extends Bundle {
   val expWidth = parameter.expWidth
@@ -61,8 +61,8 @@ class FloatAdder(val parameter: FloatAdderParameter)
   addRecFN.io.roundingMode   := io.roundingMode
   addRecFN.io.detectTininess := false.B
 
-  io.out            := fNFromRecFN(8, 24, addRecFN.io.out)
-  io.exceptionFlags := addRecFN.io.exceptionFlags
+  io.out            := Pipe(true.B, fNFromRecFN(8, 24, addRecFN.io.out), parameter.latency).bits
+  io.exceptionFlags := Pipe(true.B, addRecFN.io.exceptionFlags, parameter.latency).bits
 }
 
 object FloatCompareParameter {