[libspike] add “disable vsew > vlmul * ELEN check” patch

nix/patches/spike/0001-enforce-lanewise-order-for-unordered-reduce.patch

@@ -1,7 +1,7 @@
 From 0ad6da899c20df0ce6120bc4ebd32edf01bdcd36 Mon Sep 17 00:00:00 2001
 From: SharzyL <[email protected]>
 Date: Sun, 25 Feb 2024 01:28:18 +0800
-Subject: [PATCH 1/2] enforce lanewise order for unordered reduce
+Subject: [PATCH 1/3] enforce lanewise order for unordered reduce
 
 ---
  riscv/insns/vfredusum_vs.h |  2 +-

nix/patches/spike/0002-disable-NaN-normalization.patch

@@ -1,7 +1,7 @@
 From 09a503dc94382798a1ee2f23b4b6894a12bc8207 Mon Sep 17 00:00:00 2001
 From: SharzyL <[email protected]>
 Date: Mon, 26 Aug 2024 20:08:47 +0800
-Subject: [PATCH 2/2] disable NaN normalization
+Subject: [PATCH 2/3] disable NaN normalization
 
 ---
  riscv/v_ext_macros.h | 6 +++---

nix/patches/spike/0003-relax-vsew-vlmul-ELEN-check.patch

@@ -0,0 +1,26 @@
+From cbf79540b42a56df47df541848d47b34a0d04128 Mon Sep 17 00:00:00 2001
+From: SharzyL <[email protected]>
+Date: Tue, 3 Sep 2024 15:33:33 +0800
+Subject: [PATCH 3/3] relax 'vsew > vlmul * ELEN' check
+
+---
+ riscv/vector_unit.cc | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/riscv/vector_unit.cc b/riscv/vector_unit.cc
+index 08adc616..8fbbe16d 100644
+--- a/riscv/vector_unit.cc
++++ b/riscv/vector_unit.cc
+@@ -39,7 +39,8 @@ reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t new
+     vma = extract64(newType, 7, 1);
+
+     vill = !(vflmul >= 0.125 && vflmul <= 8)
+-           || vsew > std::min(vflmul, 1.0f) * ELEN
++           || vsew > ELEN
++           || vflmul < ((float) /* vsew_min */ 8 / ELEN)
+            || (newType >> 8) != 0;
+
+     if (vill) {
+-- 
+2.43.0
+

nix/pkgs/libspike.nix

@@ -31,6 +31,7 @@ stdenv.mkDerivation {
   patches = [
     ../patches/spike/0001-enforce-lanewise-order-for-unordered-reduce.patch
     ../patches/spike/0002-disable-NaN-normalization.patch
+    ../patches/spike/0003-relax-vsew-vlmul-ELEN-check.patch
   ];
 
   installPhase = ''

rocketv/src/CSR.scala

@@ -1701,17 +1701,20 @@ class CSR(val parameter: CSRParameter)
     val newVType     = Mux1H(
       Seq(
         (vsetvli || vsetivli) -> io.inst(0)(27, 20),
-        vsetvl                -> io.wbRegRS2.get(7, 0)
+        vsetvl                -> io.wbRegRS2.get
       )
     )
+    val newTypMSBValid: Bool = (newVType >> 8).asUInt.orR
     // todo: xLen -> vector.elen
-    val vlmulIllList =
-      Seq(0.U, 1.U, 2.U, 3.U) ++ Option.when(xLen >= 16)(7.U) ++ Option.when(xLen >= 32)(6.U) ++ Option.when(
-        xLen >= 64
-      )(5.U)
+    val vlmulIllList = Seq(0.U, 1.U, 2.U, 3.U) ++ Option.when(xLen >= 16)(7.U) ++
+      Option.when(xLen >= 32)(6.U) ++ Option.when(xLen >= 64)(5.U)
     val vlmulIll: Bool = vlmulIllList.map(_ === newVType(2, 0)).reduce(_ || _)
+    val vSewIllList = Seq(0.U) ++ Option.when(xLen >= 16)(1.U) ++
+      Option.when(xLen >= 32)(2.U) ++ Option.when(xLen >= 64)(3.U)
+    val vsewIll     = vSewIllList.map(_ === newVType(5, 3)).reduce(_ || _)
+    val vsetIll     = vlmulIll && !newTypMSBValid && vsewIll
     // vlmax = vlen * lmul / sew
-    val vlmax:    UInt = (true.B << (log2Ceil(vLen) - 6) << (newVType(2, 0) + 3.U) >> newVType(5, 3)).asUInt
+    val vlmax: UInt = (true.B << (log2Ceil(vLen) - 6) << (newVType(2, 0) + 3.U) >> newVType(5, 3)).asUInt
     // set vl
     val setVL = Mux1H(
       Seq(
@@ -1721,9 +1724,9 @@ class CSR(val parameter: CSRParameter)
         vsetivli                                        -> io.inst(0)(19, 15)
       )
     )
-    setVlReadData := Mux(io.retire(0) && io.vectorCsr.getOrElse(false.B) && vlmulIll, setVL, 0.U)
+    setVlReadData := Mux(io.retire(0) && io.vectorCsr.getOrElse(false.B) && vsetIll, setVL, 0.U)
     when(io.retire(0) && io.vectorCsr.get) {
-      when(vlmulIll) {
+      when(vsetIll) {
         vector.get.states("vl")    := setVL
         vector.get.states("vlmul") := newVType(2, 0)
         vector.get.states("vsew")  := newVType(5, 3)
@@ -1744,6 +1747,9 @@ class CSR(val parameter: CSRParameter)
       when(decoded_addr(CSRs.vxrm)) {
         vector.get.states("vxrm") := wdata
       }
+      when(decoded_addr(CSRs.vxsat)) {
+        vector.get.states("vxsat") := wdata
+      }
       when(decoded_addr(CSRs.vcsr)) {
         vector.get.states("vxrm")  := wdata(2, 1)
         vector.get.states("vxsat") := wdata(0)

script/emu/src/Main.scala

@@ -242,6 +242,16 @@ object Main:
         )
       )
     )
+
+    if finalEmuType.get == "vcs-emu-trace" then
+      val libPath    = emulator / os.up / os.up / "lib"
+      val daidirPath =
+        os.walk(libPath)
+          .filter(path => os.isDir(path))
+          .filter(path => path.segments.toSeq.last.endsWith(".daidir"))
+          .last
+      os.copy.into(daidirPath, outputPath, followLinks = true)
+
     Logger.info(s"Output saved under ${outputPath}")
   end run