Code

Support VCS in Nix#680

Code

Merged

sequencer merged 22 commits intomasterchipsalliance/t1:masterfrom vcschipsalliance/t1:vcsCopy head branch name to clipboardJul 31, 2024

+4,724-1,385

Commits

Commits on Jul 31, 2024

• [difftest] revert add rtl unexcepted quit check in difftest"

  Show description for bff6a36
  sequencer

  committed
  bff6a36

• [ipemu] Fix Testbench for X

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  c827f9b

• [rtl] don't use RRArbiter for XProp

  

  qinjun-li

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  01a995f

• [nix] remove old ipemu

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  319be56

• [ipemu] rename dpi_pre_link to verilator_shim

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  1016183

• [ipemu] move DPI logic to online_dpi crate

  

  FanShupei

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  fba5320

• [ipemu] add svdpi.h raw bindings

  

  FanShupei

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  f174038

• [ipemu] use svdpi to get time and dump waveform

  

  FanShupei

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  7d1dbfa

• [ipemu] add sv_vpi_user.h raw bindings

  

  FanShupei

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  52e16e5

• [ipemu] support get simulation time through vpi

  

  FanShupei

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  2bbfbe4

• [ipemu] rename cosim_init -> t1_cosim_init

  

  FanShupei

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  14a9395

• [ipemu] mark cosim_init as context

  

  FanShupei

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  bdc232c

• [ipemu] remember cosim_init scope

  

  FanShupei

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  a08e8e1

• [ipemu] remove default vlen/dlen value

  Show description for 2fc7ee8
  

  Avimitin

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  2fc7ee8

• [ipemu] add fsdbdump support in TestBench

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  a5c19ca

• [ipemu] add VCS DPI library build target

  

  FanShupei

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  ddf18fa

• [nix] refactor nix for vcs+verilator emulator

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  6507ca6

• [nix] add derivation for vcs artifacts

  

  Avimitin

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  3594eb4

• [ci] add VCS CI

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  59a0544

• [ci] refactor workflows into multiple runs

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  22a4ac9

• [ci] update test case cycle data

  

  github-actions

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  1840074

• [ci] Verilog won't block PR CI anymore

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  b41af67