[rtl] fix mask update in lane.

chipsalliance · Dec 16, 2024 · f1e1608 · f1e1608
1 parent 8f13557
commit f1e1608
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Showing 2 changed files with 4 additions and 5 deletions.
diff --git a/t1/src/Lane.scala b/t1/src/Lane.scala
@@ -686,7 +686,7 @@ class Lane(val parameter: LaneParameter) extends Module with SerializableModule[
     val maskFailure:    Bool = stage0.updateLaneState.maskExhausted && stage0.enqueue.fire
     // update mask register
     when(maskUpdateFire) {
-      record.mask.bits := DontCare
+      record.mask.bits := maskDataVec(index)
     }
     when(maskUpdateFire ^ maskFailure) {
       record.mask.valid := maskUpdateFire

diff --git a/t1/src/T1.scala b/t1/src/T1.scala
@@ -964,10 +964,9 @@ class T1(val parameter: T1Parameter)
       probe.valid := write.fire && write.bits.mask.orR
       probe.bits  := write.bits.instructionIndex
     }
-    probeWire.instructionValid   := maskAnd(
-      !slots.last.state.wMaskUnitLast && !slots.last.state.idle,
-      indexToOH(slots.last.record.instructionIndex, parameter.chainingSize)
-    ).asUInt
+    probeWire.instructionValid   := slots
+      .map(s => maskAnd(!s.state.idle, indexToOH(s.record.instructionIndex, parameter.chainingSize)).asUInt)
+      .reduce(_ | _)
     probeWire.responseCounter    := responseCounter
     probeWire.laneProbes.zip(laneVec).foreach { case (p, l) => p := probe.read(l.laneProbe) }
     probeWire.lsuProbe           := probe.read(lsu.lsuProbe)