[ipemu] filter 64-bit width instructions in t1 emu coverage flow

t1emu/src/TestBench.scala

@@ -285,7 +285,55 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
       scoreboard.bits  := 0.U
     }
   }
-  generator.parameter.decoderParam.allInstructions.map { instruction: Instruction =>
+
+  // coverage
+  // unsupported 64-bit instructions for 32-bit xlen
+  val zve32f = Seq(
+    // format: off
+    "vfadd.vf", "vfadd.vv", "vfclass.v", "vfcvt.f.x.v", 
+    "vfcvt.f.xu.v", "vfcvt.rtz.x.f.v", "vfcvt.rtz.xu.f.v", "vfcvt.x.f.v", 
+    "vfcvt.xu.f.v", "vfdiv.vf", "vfdiv.vv", "vfmacc.vf",
+    "vfmacc.vv", "vfmadd.vf", "vfmadd.vv", "vfmax.vf",
+    "vfmax.vv", "vfmerge.vfm", "vfmin.vf", "vfmin.vv",
+    "vfmsac.vf", "vfmsac.vv", "vfmsub.vf", "vfmsub.vv",
+    "vfmul.vf", "vfmul.vv", "vfmv.f.s", "vfmv.s.f",
+    "vfmv.v.f", "vfnmacc.vf", "vfnmacc.vv", "vfnmadd.vf",
+    "vfnmadd.vv", "vfnmsac.vf", "vfnmsac.vv", "vfnmsub.vf",
+    "vfnmsub.vv", "vfrdiv.vf", "vfrec7.v", "vfredmax.vs",
+    "vfredmin.vs", "vfredosum.vs", "vfredusum.vs", "vfrsqrt7.v",
+    "vfrsub.vf", "vfsgnj.vf", "vfsgnj.vv", "vfsgnjn.vf",
+    "vfsgnjn.vv", "vfsgnjx.vf", "vfsgnjx.vv", "vfsqrt.v",
+    "vfsub.vf", "vfsub.vv", "vmfeq.vf", "vmfeq.vv",
+    "vmfge.vf", "vmfgt.vf", "vmfle.vf", "vmfle.vv", 
+    "vmflt.vf", "vmflt.vv", "vmfne.vf", "vmfne.vv"
+    // format: on
+  )
+  val zve64f = Seq(
+    // format: off
+    "vfncvt.f.f.w", "vfncvt.f.x.w", "vfncvt.f.xu.w", "vfncvt.rod.f.f.w", "vfncvt.rtz.x.f.w", "vfncvt.rtz.xu.f.w", "vfncvt.x.f.w", "vfncvt.xu.f.w",
+    "vfwadd.vf", "vfwadd.vv", "vfwadd.wf", "vfwadd.wv",
+    "vfwcvt.f.f.v", "vfwcvt.f.x.v", "vfwcvt.f.xu.v", "vfwcvt.rtz.x.f.v", "vfwcvt.rtz.xu.f.v", "vfwcvt.x.f.v", "vfwcvt.xu.f.v",
+    "vfwmacc.vf", "vfwmacc.vv", "vfwmsac.vf", "vfwmsac.vv",
+    "vfwmul.vf", "vfwmul.vv", "vfwnmacc.vf", "vfwnmacc.vv",
+    "vfwnmsac.vf", "vfwnmsac.vv", "vfwredosum.vs", "vfwredusum.vs",
+    "vfwsub.vf", "vfwsub.vv", "vfwsub.wf", "vfwsub.wv", 
+    // format: on
+  )
+  val zve64x = Seq(
+    // format: off
+    "vl1re64.v", "vl2re64.v", "vl4re64.v", "vl8re64.v", 
+    "vle64.v", "vle64ff.v", "vloxei64.v", "vlse64.v", "vluxei64.v",
+    "vse64.v", "vsoxei64.v", "vsse64.v", "vsuxei64.v", 
+    "vsext.vf8", "vzext.vf8"
+    // format: on
+  )
+  generator.parameter.decoderParam.allInstructions.filter { instruction: Instruction =>
+    // format: off
+    !(zve64x.contains(instruction.name) && generator.parameter.xLen == 32) &&
+    !(zve64f.contains(instruction.name) && generator.parameter.xLen == 32 && generator.parameter.fpuEnable) &&
+    !((zve32f ++ zve64f).contains(instruction.name) && !generator.parameter.fpuEnable)
+    // format: on
+  }.map { instruction: Instruction =>
     val issueMatch = Sequence.BoolSequence(issue.instruction === BitPat("b" + instruction.encoding.toString))
     CoverProperty(issueMatch, label = Some(s"t1_cover_issue_${instruction.name}"))
   }